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Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA and Voltage Output DAC, Dynamic Power Control, HART Connectivity
AD5755-1
FEATURES
16-bit resolution and monotonicity Dynamic power control for thermal management Current and voltage output pins connectable to a single terminal Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, or 0 mA to 24 mA 0.05% total unadjusted error (TUE) maximum Voltage output ranges (with 20% overrange): 0 V to 5 V, 0 V to 10 V, 5 V, and 10 V 0.04% total unadjusted error (TUE) maximum User programmable offset and gain On-chip diagnostics On-chip reference (10 ppm/C maximum) -40C to +105C temperature range
dissipation in current mode. This is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5755-1. The part uses a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standard SPI, QSPITM, MICROWIRETM, DSP, and microcontroller interface standards. The interface also features optional CRC-8 packet error checking, as well as a watchdog timer that monitors activity on the interface.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. Dynamic power control for thermal management. 16-bit performance. Multichannel. HART compliant.
APPLICATIONS
Process control Actuator control PLCs HART network connectivity
COMPANION PRODUCTS
Product Family: AD5755, AD5757 External References: ADR445, ADR02 Digital Isolators: ADuM1410, ADuM1411 Power: ADP2302, ADP2303 Additional companion products on the AD5755-1 product page
GENERAL DESCRIPTION
The AD5755-1 is a quad, voltage and current output DAC that operates with a power supply range from -26.4 V to +33 V. On-chip dynamic power control minimizes package power
FUNCTIONAL BLOCK DIAGRAM
AVCC 5.0V AVSS -15V/0V AGND AVDD +15V SWx VBOOST_x
DVDD DGND LDAC SCLK SDIN SYNC SDO CLEAR FAULT ALERT AD1 AD0 DAC CHANNEL A REFOUT REFIN REFERENCE DAC CHANNEL B DAC CHANNEL C DAC CHANNEL D GAIN REG A OFFSET REG A DIGITAL INTERFACE + DAC A DC-TO-DC CONVERTER
7.4V TO 29.5V
IOUT_x CURRENT AND VOLTAGE OUTPUT RANGE SCALING RSET_x CHARTx +VSENSE_x VOUT _x
NOTES 1. x = A, B, C, AND D.
Figure 1.
Rev. A
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09226-101
AD5755-1
AD5755-1 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Companion Products ....................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Detailed Functional Block Diagram .............................................. 3 Specifications..................................................................................... 4 AC Performance Characteristics ................................................ 7 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings.......................................................... 11 ESD Caution................................................................................ 11 Pin Configuration and Function Descriptions........................... 12 Typical Performance Characteristics ........................................... 15 Voltage Outputs .......................................................................... 15 Current Outputs ......................................................................... 19 DC-to-DC Block......................................................................... 23 Reference ..................................................................................... 24 General......................................................................................... 25 Terminology .................................................................................... 26 Theory of Operation ...................................................................... 28 DAC Architecture....................................................................... 28 Power-On State of the AD5755-1............................................. 28 Serial Interface ............................................................................ 29 Transfer Function ....................................................................... 29 Registers ........................................................................................... 30 Programming Sequence to Write/Enable the Output Correctly ...................................................................................... 31 Changing and Reprogramming the Range ............................. 31 Data Registers ............................................................................. 32 Control Registers........................................................................ 34 Readback Operation .................................................................. 37 Device Features............................................................................... 39 Output Fault................................................................................ 39 Voltage Output Short-Circuit Protection................................ 39 Digital Offset and Gain Control............................................... 39 Status Readback During a Write .............................................. 39 Asynchronous Clear................................................................... 40 Packet Error Checking............................................................... 40 Watchdog Timer......................................................................... 40 Output Alert................................................................................ 40 Internal Reference ...................................................................... 40 External Current Setting Resistor ............................................ 40 HART ........................................................................................... 41 Digital Slew Rate Control.......................................................... 41 Power Dissipation control......................................................... 42 DC-to-DC Converters............................................................... 42 AICC Supply Requirements--Static .......................................... 43 AICC Supply Requirements--Slewing ...................................... 43 Applications Information .............................................................. 45 Voltage and Current Output Ranges on the Same Terminal 45 Current Output Mode with Internal RSET................................ 45 Precision Voltage Reference Selection..................................... 45 Driving Inductive Loads............................................................ 46 Transient Voltage Protection .................................................... 46 Microprocessor Interfacing....................................................... 46 Layout Guidelines....................................................................... 46 Galvanically Isolated Interface ................................................. 47 Outline Dimensions ....................................................................... 48 Ordering Guide .......................................................................... 48
REVISION HISTORY
5/11--Rev. 0 to Rev. A Removed Endnote 6 (Table 1)......................................................... 6 Changed AVDD Minimum Value from 10.8 V to 9 V................... 6 Changed AISS Minimum Value from -1.4 mA to -1.7 mA ........ 7 Changed AVDD Voltage in Pin 19 Description............................ 13 Changes to Ordering Guide .......................................................... 48 4/11--Revision 0: Initial Version
Rev. A | Page 2 of 48
AD5755-1 DETAILED FUNCTIONAL BLOCK DIAGRAM
AVCC 5.0V AVSS -15V/0V AGND AVDD +15V SWA VBOOST_A
DVDD DGND LDAC CLEAR SCLK SDIN SYNC SDO FAULT
POWER-ON RESET
DC-TO-DC CONVERTER POWER CONTROL 16 16 7.4V TO 29.5V VSEN1 REG R2 VSEN2
INPUT SHIFT REGISTER AND CONTROL
INPUT REG A GAIN REG A OFFSET REG A
+
DAC REG A
DAC A
R3
IOUT_A
STATUS REGISTER ALERT WATCHDOG TIMER (SPI ACTIVITY) VREF REFERENCE BUFFERS
R1
RSET_A CHARTA
REFOUT REFIN
DAC CHANNEL A
VOUT RANGE SCALING
+VSENSE_A VOUT_A
IOUT_B, IOUT_C, IOUT_D
AD1 AD0
AD5755-1
DAC CHANNEL B DAC CHANNEL C DAC CHANNEL D SWB, SWC, SWD VBOOST_B, VBOOST_C, VBOOST_D
RSET_B, RSET_C, RSET_D CHARTB, CHARTC, CHARTD +VSENSE_B, +VSENSE_C, +VSENSE_D
09226-001
VOUT_B, VOUT_C, VOUT_D
Figure 2.
Rev. A | Page 3 of 48
AD5755-1 SPECIFICATIONS
AVDD = VBOOST_x = 15 V; AVSS = -15 V/0 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 k, CL = 220 pF; current outputs: RL = 300 ; all specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter 1 VOLTAGE OUTPUT Output Voltage Ranges Min 0 0 -5 -10 0 0 -6 -12 ACCURACY BIPOLAR SUPPLY Resolution Total Unadjusted Error (TUE) TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Zero-Scale Error Zero-Scale TC 2 Bipolar Zero Error Bipolar Zero TC2 Offset Error Offset TC2 Gain Error Gain TC2 Full-Scale Error Full-Scale TC2 ACCURACY UNIPOLAR SUPPLY2 Total Unadjusted Error (TUE) Relative Accuracy (INL) 3 Differential Nonlinearity (DNL) Zero-Scale Error Offset Error Gain Error Full-Scale Error OUTPUT CHARACTERISTICS2 Headroom Footroom Output Voltage Drift vs. Time Short-Circuit Current Load Typ Max 5 10 +5 +10 6 12 +6 +12 Unit V V V V V V V V Test Conditions/Comments
AVDD must have minimum 2.2 V headroom on output AVDD/AVSS must have minimum 2.2 V headroom on output AVDD must have minimum 2.2 V headroom on output AVDD/AVSS must have minimum 2.2 V headroom on output AVSS = -15 V, loaded and unloaded
16 -0.04 -0.03 -0.006 -0.008 -1 -0.03 -0.03 -0.03 -0.03 -0.03
0.0032 35 0.0012 0.0012 0.002 2 0.002 1 0.002 2 0.004 3 0.002 2 0.025
+0.04 +0.03 +0.006 +0.008 +1 +0.03 +0.03 +0.03 +0.03 +0.03
Bits % FSR % FSR ppm FSR % FSR % FSR LSB % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR % FSR LSB % FSR % FSR % FSR % FSR V V ppm FSR mA k
TA = 25C Drift after 1000 hours, TJ = 150C 0 V to 5 V, 0 V to 10 V, 5 V, 10 V ranges On overranges Guaranteed monotonic
AVSS = 0 V -0.06 -0.009 -1 -0.07 -0.07 -0.06 +0.06 +0.009 +1 +0.07 +0.07 +0.06 2.2 1.4
Guaranteed monotonic
+0.22 0.025 0.015 0.015 1 0.7 20
12/6 1
16/8
Bipolar output ranges Drift after 1000 hours, 3/4 scale output, TJ = 150C, AVSS = -15 V Programmable by user, defaults to 16 mA typical level For specified performance
Rev. A | Page 4 of 48
AD5755-1
Parameter 1 Capacitive Load Stability DC Output Impedance DC PSRR DC Crosstalk CURRENT OUTPUT Output Current Ranges Min Typ Max 10 2 Unit nF F V/V V mA mA mA Bits Assumes ideal resistor -0.05 -0.006 -1 -0.05 -0.05 -0.05 0.009 100 +0.05 +0.006 +1 +0.05 +0.05 +0.05 % FSR ppm FSR % FSR LSB % FSR ppm FSR/C % FSR ppm FSR/C % FSR ppm FSR/C % FSR % FSR % FSR ppm FSR % FSR % FSR LSB % FSR % FSR ppm FSR/C % FSR % FSR ppm FSR/C % FSR % FSR ppm FSR/C % FSR V Drift after 1000 hours, 3/4 scale output, TJ = 150C External RSET Internal RSET The dc-to-dc converter has been characterized with a maximum load of 1 k, chosen such that compliance is not exceeded; see Figure 53 and DC-DC MaxV bits in Table 25 Drift after 1000 hours, TJ = 150C Guaranteed monotonic Test Conditions/Comments External compensation capacitor of 220 pF connected
0.06 50 24 0 0 4 16 24 20 20
Resolution ACCURACY (EXTERNAL RSET) Total Unadjusted Error (TUE) TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error Full-Scale TC2 DC Crosstalk ACCURACY (INTERNAL RSET) Total Unadjusted Error (TUE) 4 , 5 TUE Long-Term Stability Relative Accuracy (INL) Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error4, 5 Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error4, 5 Full-Scale TC2 DC Crosstalk5 OUTPUT CHARACTERISTICS2 Current Loop Compliance Voltage Output Current Drift vs. Time
0.005 4 0.004 3 0.008 5 0.0005
External RSET
-0.14 -0.11 -0.006 -0.004 -1 -0.05 -0.04 -0.12 -0.06 -0.14 -0.1
0.009 180
+0.14 +0.11 +0.006 +0.004 +1 +0.05 +0.04 +0.12 +0.06 +0.14 +0.1
TA = 25C Drift after 1000 hours, TJ = 150C TA = 25C Guaranteed monotonic TA = 25C
0.007 6 0.002 9 0.007 14 -0.011 VBOOST_x - 2.4 90 140
TA = 25C
TA = 25C Internal RSET
VBOOST_x - 2.7
Resistive Load
1000
ppm FSR ppm FSR
Output Impedance DC PSRR
100 0.02
1
M A/V
Rev. A | Page 5 of 48
AD5755-1
Parameter 1 REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Reference Output Output Voltage Reference TC2 Output Noise (0.1 Hz to 10 Hz)2 Noise Spectral Density2 Output Voltage Drift vs. Time2 Capacitive Load2 Load Current Short-Circuit Current Line Regulation2 Load Regulation2 Thermal Hysteresis2 DC-TO-DC Switch Switch On Resistance Switch Leakage Current Peak Current Limit Oscillator Oscillator Frequency Maximum Duty Cycle DIGITAL INPUTS2 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance DIGITAL OUTPUTS2 SDO, ALERT VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance FAULT VOL, Output Low Voltage VOL, Output Low Voltage VOH, Output High Voltage POWER REQUIREMENTS AVDD AVSS DVDD AVCC Min Typ Max Unit Test Conditions/Comments
4.95 45 4.995 -10
5 150 5 5 7 100 180 1000 9 10 3 95 160 5
5.05
V M V ppm/C V p-p nV/Hz ppm nF mA mA ppm/V ppm/mA ppm ppm
For specified performance
5.005 +10
TA = 25C
At 10 kHz Drift after 1000 hours, TJ = 150C See Figure 64 See Figure 65 See Figure 64 First temperature cycle Second temperature cycle
0.425 10 0.8 11.5 13 89.6 2 -1 2.6 0.8 +1 14.5
nA A MHz % V V A pF This oscillator is divided down to give the dc-to-dc converter switching frequency At 410 kHz dc-to-dc switching frequency JEDEC compliant
Per pin Per pin
0.4 DVDD - 0.5 -1 2.5 +1
V V A pF
Sinking 200 A Sourcing 200 A
0.4 0.6 3.6 9 -26.4 2.7 4.5 33 -10.8/0 5.5 5.5
V V V V V V V
10 k pull-up resistor to DVDD At 2.5 mA 10 k pull-up resistor to DVDD
Rev. A | Page 6 of 48
AD5755-1
Parameter 1 AIDD Min Typ 8.6 7 -8.8 Max 10.5 7.5 Unit mA mA mA mA mA mA mA mA mW Test Conditions/Comments Voltage output mode on all channels, output unloaded, over supplies Current output mode on all channels Voltage output mode on all channels, output unloaded, over supplies Current output mode on all channels VIH = DVDD, VIL = DGND, internal oscillator running, over supplies Output unloaded, over supplies Per channel, voltage output mode, output unloaded, over supplies Per channel, current output mode, 0 mA output AVDD = +15 V, AVSS = -15 V, dc-to-dc converter enable, current output mode, outputs disabled
AISS
-11 -1.7
DICC AICC IBOOST IBOOST 6 Power Dissipation
1 2
9.2
11 1 2.7 1
173
Temperature range: -40C to +105C; typical at +25C. Guaranteed by design and characterization; not production tested. 3 For voltage output ranges in unipolar supply mode, the INL and TUE are measured beginning from Code 4096. 4 For current outputs with internal RSET, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled loaded with the same code. 5 See the Current Output Mode with Internal RSET section for more explanation of the dc crosstalk. 6 Efficiency plots in Figure 55, Figure 56, Figure 57, and Figure 58 include the IBOOST quiescent current
AC PERFORMANCE CHARACTERISTICS
AVDD = VBOOST_x = 15 V; AVSS = -15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 2 k, CL = 220 pF; current outputs: RL = 300 ; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter 1 DYNAMIC PERFORMANCE Voltage Output Output Voltage Settling Time Min Typ Max Unit Test Conditions/Comments
11 18 13
Slew Rate Power-On Glitch Energy Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Digital Feedthrough DAC to DAC Crosstalk Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise Spectral Density AC PSRR Current Output Output Current Settling Time
1.9 150 6 25 1 2 0.15 150 83
s s s V/s nV-sec nV-sec mV nV-sec nV-sec LSB p-p nV/Hz dB
5 V step to 0.03% FSR, 0 V to 5 V range 10 V step to 0.03% FSR, 0 V to 10 V range 100 mV step to 1 LSB (16-bit LSB), 0 V to 10 V range 0 V to 10 V range
0 V to 10 V range 16-bit LSB, 0 V to 10 V range Measured at 10 kHz, midscale output, 0 V to 10 V range 200 mV 50 Hz/60 Hz sine wave superimposed on power supply voltage To 0.1% FSR (0 mA to 24 mA) See Figure 49, Figure 50, and Figure 51 16-bit LSB, 0 mA to 24 mA range Measured at 10 kHz, midscale output, 0 mA to 24 mA range
Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise Spectral Density
1
15 See test conditions/ comments 0.15 0.5
s ms LSB p-p nA/Hz
Guaranteed by design and characterization; not production tested.
Rev. A | Page 7 of 48
AD5755-1
TIMING CHARACTERISTICS
AVDD = VBOOST_x = 15 V; AVSS = -15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 k, CL = 220 pF; current outputs: RL = 300 ; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
Parameter1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 Limit at TMIN, TMAX 33 13 13 13 13 198 5 5 20 5 10 500 See the AC Performance Characteristics section 10 5 40 21 5 500 800 20 5 Unit ns min ns min ns min ns min ns min ns min ns min ns min s min s min ns min ns max s max ns min s max ns max s min s min ns min ns min s min s min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th/32nd SCLK falling edge to SYNC rising edge (see Figure 78) SYNC high time Data setup time Data hold time SYNC rising edge to LDAC falling edge (all DACs updated or any channel has digital slew rate control enabled) SYNC rising edge to LDAC falling edge (single DAC updated) LDAC pulse width low LDAC falling edge to DAC output response time DAC output settling time CLEAR high time CLEAR activation time SCLK rising edge to SDO valid SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated) SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated) LDAC falling edge to SYNC rising edge RESET pulse width SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated) SYNC high to next SYNC low (digital slew rate control disabled) (single DAC updated)
t10 t11 t12 t13 t14 t15 t16 t17 t18 t194
1 2 3
Guaranteed by design and characterization; not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. See Figure 3, Figure 4, Figure 5, and Figure 6. 4 This specification applies if LDAC is held low during the write cycle; otherwise, see t9.
Rev. A | Page 8 of 48
AD5755-1
Timing Diagrams
t1
SCLK 1 2 24
t6 t4
SYNC
t3
t2 t5
t7
SDIN MSB
t8
LSB
t19
t10
LDAC
t9
t10
t17
VOUT_x
t12 t11
LDAC = 0
t12
VOUT_x
t16 t13
CLEAR
t14
VOUT_x
Figure 3. Serial Interface Timing Diagram
SCLK
1
24
1
24
t6
SYNC
SDIN
MSB
LSB
MSB
LSB
INPUT WORD SPECIFIES REGISTER TO BE READ SDO MSB LSB MSB
NOP CONDITION
LSB
09226-003
UNDEFINDED
t15
SELECTED REGISTER DATA CLOCKED OUT
Figure 4. Readback Timing Diagram
Rev. A | Page 9 of 48
09226-002
RESET
t18
AD5755-1
1 SCLK 2 MSB
SYNC
SDIN
R/W
DUT_ AD1
DUT_ AD0
X
X
X
DB15
DB14
DB1
DB0
SDO
SDO DISABLED
SDO_ ENAB
STATUS
STATUS
STATUS
STATUS
09226-004
Figure 5. Status Readback During Write
200A IOL
TO OUTPUT PIN
CL 50pF 200A IOH
VOH (MIN) OR VOL (MAX)
09226-005
Figure 6. Load Circuit for SDO Timing Diagram
Rev. A | Page 10 of 48
AD5755-1 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4.
Parameter AVDD, VBOOST_x to AGND, DGND AVSS to AGND, DGND AVDD to AVSS AVCC to AGND DVDD to DGND Digital Inputs to DGND Digital Outputs to DGND REFIN, REFOUT to AGND VOUT_x to AGND +VSENSE_x to AGND IOUT_x to AGND SWx to AGND AGND, GNDSWx to DGND Operating Temperature Range (TA) Industrial1 Storage Temperature Range Junction Temperature (TJ max) 64-Lead LFCSP JA Thermal Impedance2 Power Dissipation Lead Temperature Soldering
1
Rating -0.3 V to +33 V +0.3 V to -28 V -0.3 V to +60 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to DVDD + 0.3 V or +7 V (whichever is less) -0.3 V to DVDD + 0.3 V or +7 V (whichever is less) -0.3 V to AVDD + 0.3 V or +7 V (whichever is less) AVSS to VBOOST_x or 33 V if using the dc-to-dc circuitry AVSS to VBOOST_x or 33 V if using the dc-to-dc circuitry AVSS to VBOOST_x or 33 V if using the dc-to-dc circuitry -0.3 to +33 V -0.3 V to +0.3 V -40C to +105C -65C to +150C 125C 20C/W (TJ max - TA)/JA JEDEC industry standard J-STD-020
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
2
Power dissipated on chip must be derated to keep the junction temperature below 125C. Based on a JEDEC 4-layer test board.
Rev. A | Page 11 of 48
AD5755-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RSET_C RSET_D REFOUT REFIN COMPLV_D CHARTD +VSENSE_D COMPDCDC_D VBOOST_D VOUT_D IOUT_D AVSS COMPLV_C CHARTC +VSENSE_C VOUT_C
PIN 1 INDICATOR RSET_B RSET_A REFGND REFGND AD0 AD1 SYNC SCLK SDIN SDO DVDD DGND LDAC CLEAR ALERT FAULT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AD5755-1
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
COMPDCDC_C IOUT_C VBOOST_C AVCC SWC GNDSWC GNDSWD SWD AVSS SWA GNDSWA GNDSWB SWB AGND VBOOST_B IOUT_B
Figure 7. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3, 4 5 6 7 8 9 10 11 12 13 Mnemonic RSET_B RSET_A REFGND AD0 AD1 SYNC SCLK SDIN SDO DVDD DGND LDAC Description An external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the IOUT_B temperature drift performance. See the Device Features section. An external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the IOUT_A temperature drift performance. See the Device Features section. Ground Reference Point for Internal Reference. Address Decode for the Device Under Test (DUT) on the Board. Address Decode for the DUT on the Board. Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the rising edge of SCLK. This operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5. Digital Supply. The voltage range is from 2.7 V to 5.5 V. Digital Ground. Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The LDAC pin must not be left unconnected. Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more information. When CLEAR is active, the DAC output register cannot be written to.
14
CLEAR
Rev. A | Page 12 of 48
09266-006
NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO THE POTENTIAL OF THE AVSS PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.
POC RESET AVDD COMPLV_A CHARTA +VSENSE_A COMPDCDC_A VBOOST_A VOUT_A IOUT_A AVSS COMPLV_B CHARTB +VSENSE_B VOUT_B COMPDCDC_B
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AD5755-1
Pin No. 15 16 Mnemonic ALERT FAULT Description Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a predetermined time. See the Device Features section for more information. Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in voltage mode is detected, a PEC error is detected, or an overtemperature is detected (see the Device Features section). Open-drain output. Power-On Condition. This pin determines the power-on condition and is read during power-on or, alternatively, after a device reset. If POC = 0, the device is powered up with the voltage and current channels in tristate mode. If POC = 1, the device is powered up with a 30 k pull-down resistor to ground on the voltage output channel, and the current channel is in tristate mode. Hardware Reset, Active Low Input. Positive Analog Supply. The voltage range is from 9 V to 33 V. Optional Compensation Capacitor Connection for VOUT_A Output Buffer. Connecting a 220 pF capacitor between this pin and the VOUT_A pin allows the voltage output to drive up to 2 F. Note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. HART Input Connection for DAC Channel A. Sense Connection for the Positive Voltage Output Load Connection for VOUT_A. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and the AICC Supply Requirements--Slewing sections in the Device Features section for more information). Supply for Channel A Current Output Stage (see Figure 73). This is also the supply for the VOUT_x stage, which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 80. Buffered Analog Output Voltage for DAC Channel A. Current Output Pin for DAC Channel A. Negative Analog Supply. Voltage range is from -10.8 V to -26.4 V. Optional Compensation Capacitor Connection for VOUT_B Output Buffer. Connecting a 220 pF capacitor between this pin and the VOUT_B pin allows the voltage output to drive up to 2 F. Note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. HART Input Connection for DAC Channel B. Sense Connection for the Positive Voltage Output Load Connection for VOUT_B. Buffered Analog Output Voltage for DAC Channel B. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements--Slewing sections in the Device Features section for more information). Current Output Pin for DAC Channel B. Supply for Channel B Current Output Stage (see Figure 73). This is also the supply for the VOUT_x stage, which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 80. Ground Reference Point for Analog Circuitry. This must be connected to 0 V. Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 80. Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 80. Negative Analog Supply Pin. The voltage range is from -10.8 V to -26.4 V. This pin can be connected to 0 V if using the device in unipolar supply mode. Switching Output for Channel D DC-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 80. Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground. Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground. Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 80. Supply for DC-to-DC Circuitry.
Rev. A | Page 13 of 48
17
POC
18 19 20
RESET AVDD COMPLV_A
21 22 23
CHARTA +VSENSE_A COMPDCDC_A
24
VBOOST_A
25 26 27 28
VOUT_A IOUT_A AVSS COMPLV_B
29 30 31 32
CHARTB +VSENSE_B VOUT_B COMPDCDC_B
33 34
IOUT_B VBOOST_B
35 36 37 38 39 40 41 42 43 44 45
AGND SWB GNDSWB GNDSWA SWA AVSS SWD GNDSWD GNDSWC SWC AVCC
AD5755-1
Pin No. 46 Mnemonic VBOOST_C Description Supply for Channel C Current Output Stage (see Figure 73). This is also the supply for the VOUT_x stage, which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 80. Current Output Pin for DAC Channel C. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements--Slewing sections in the Device Features section for more information). Buffered Analog Output Voltage for DAC Channel C. Sense Connection for the Positive Voltage Output Load Connection for VOUT_C. HART Input Connection for DAC Channel C. Optional Compensation Capacitor Connection for VOUT_C Output Buffer. Connecting a 220 pF capacitor between this pin and the VOUT_C pin allows the voltage output to drive up to 2 F. Note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. Negative Analog Supply Pin. Current Output Pin for DAC Channel D. Buffered Analog Output Voltage for DAC Channel D. Supply for Channel D Current Output Stage (see Figure 73). This is also the supply for the VOUT_x stage, which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 80. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements--Slewing sections in the Device Features section for more information). Sense Connection for the Positive Voltage Output Load Connection for VOUT_D. HART Input Connection for DAC Channel D Optional Compensation Capacitor Connection for VOUT_D Output Buffer. Connecting a 220 pF capacitor between this pin and the VOUT_D pin allows the voltage output to drive up to 2 F. Note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. External Reference Voltage Input. Internal Reference Voltage Output. It is recommended to place a 0.1 F capacitor between REFOUT and REFGND. An external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the IOUT_D temperature drift performance. See the Device Features section. An external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the IOUT_C temperature drift performance. See the Device Features section. Exposed Pad. This exposed pad should be connected to the potential of the AVSS pin, or, alternatively, it can be left electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.
47 48
IOUT_C COMPDCDC_C
49 50 51 52
VOUT_C +VSENSE_C CHARTC COMPLV_C
53 54 55 56
AVSS IOUT_D VOUT_D VBOOST_D
57
COMPDCDC_D
58 59 60
+VSENSE_D CHARTD COMPLV_D
61 62 63 64
REFIN REFOUT RSET_D RSET_C EPAD
Rev. A | Page 14 of 48
AD5755-1 TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE OUTPUTS
0.0015 AVDD = +15V 10V RANGE 5V RANGE AVSS = -15V +10V RANGE TA = 25C +5V RANGE +10V RANGE WITH DCDC
INL ERROR (%FSR)
0.0015 0.0010
0.0010
INL ERROR (%FSR)
0.0005
0.0005
0
+5V RANGE MAX INL 5V RANGE MAX INL +5V RANGE MIN INL 5V RANGE MIN INL AVDD = +15V AVSS = -15V OUTPUT UNLOADED
+10V RANGE MAX INL 10V RANGE MAX INL +10V RANGE MIN INL 10V RANGE MIN INL
0
-0.0005
-0.0005
-0.0010
09226-127
09226-023
-0.0010
0
10k
20k
30k CODE
40k
50k
60k
-0.0015 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
Figure 8. Integral Nonlinearity Error vs. DAC Code
1.0 0.8 0.6
DNL ERROR (LSB)
Figure 11. Integral Nonlinearity Error vs. Temperature
1.0
AVDD = +15V 10V RANGE 5V RANGE AVSS = -15V +10V RANGE TA = 25C +5V RANGE +10V RANGE WITH DCDC
0.8 0.6
DNL ERROR (%FSR)
AVDD = +15V AVSS = -15V ALL RANGES
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
09226-024
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
09226-128
DNL ERROR MAX DNL ERROR MIN
-1.0 0 10k 20k 30k CODE 40k 50k 60k
-1.0 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
Figure 9. Differential Nonlinearity Error vs. DAC Code
0.006
TOTAL UNADJUSTED ERROR (%FSR)
Figure 12. Differential Nonlinearity Error vs. Temperature
0.012
TOTAL UNADJUSTED ERROR (%FSR)
0.004 0.002 0 -0.002 -0.004 -0.006 -0.008 -0.010
10V RANGE AVDD = +15V 5V RANGE AVSS = -15V +10V RANGE TA = 25C +5V RANGE +10V RANGE WITH DCDC
0.010 0.008 0.006 0.004 0.002 0 -0.002
+5V RANGE +10V RANGE 5V RANGE 10V RANGE AVDD = +15V AVSS = -15V OUTPUT UNLOADED
0
10k
20k
30k CODE
40k
50k
60k
09226-025
-0.006 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
Figure 10. Total Unadjusted Error vs. DAC Code
Figure 13. Total Unadjusted Error vs. Temperature
Rev. A | Page 15 of 48
09226-129
-0.004
AD5755-1
0
TOTAL UNADJUSTED ERROR (%FSR)
0.0025 0.0020
BIPOLAR ZERO ERROR (%FSR)
-0.005 -0.010 -0.015 -0.020 -0.025 -0.030 -0.035 -40 +5V RANGE +12V RANGE AVDD = +15V AVSS = 0V OUTPUT UNLOADED
0.0015 0.0010 0.0005 0 -0.0005 -0.0010 -0.0015 -0.0020 -40 5V RANGE 10V RANGE AVDD = +15V AVSS = -15V OUTPUT UNLOADED
09226-134
-20
0
20
40
60
80
100
09226-130
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 14. Total Unadjusted Error vs. Temperature, Single Supply
0.012 0.010
FULL-SCALE ERROR (%FSR)
0.010
Figure 17. Bipolar Zero Error vs. Temperature
0.008 0.006 0.004 0.002 0 -0.002
+5V RANGE +10V RANGE 5V RANGE 10V RANGE
GAIN ERROR (%FSR)
0.008 0.006 0.004 0.002 0 -0.002
09226-132
+5V RANGE +10V RANGE 5V RANGE 10V RANGE AVDD = +15V AVSS = -15V OUTPUT UNLOADED
AVDD = +15V AVSS = -15V OUTPUT UNLOADED
-0.006 -40
-20
0
20
40
60
80
100
-0.006 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 15. Full-Scale Error vs. Temperature
0.0015 0.0010 0.0005
OFFSET (%FSR)
ZERO-SCALE ERROR (%FSR)
Figure 18. Gain Error vs. Temperature
0.0015 0.0010 0.0005 0 -0.0005 -0.0010 -0.0015 -0.0020 -40 +5V RANGE +10V RANGE 5V RANGE 10V RANGE AVDD = +15V AVSS = -15V OUTPUT UNLOADED -20 0 20 40 60 80 100
0 -0.0005 -0.0010 -0.0015 -0.0020 -0.0025 -40 +5V RANGE +10V RANGE AVDD = +15V AVSS = -15V OUTPUT UNLOADED
09226-133
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 16. Offset Error vs. Temperature
Figure 19. Zero-Scale Error vs. Temperature
Rev. A | Page 16 of 48
09226-136
09226-135
-0.004
-0.004
AD5755-1
0.0020 0.0015
0.0020 0.0015
OUTPUT VOLTAGE DELTA (V)
8mA LIMIT, CODE = 0xFFFF 16mA LIMIT, CODE = 0xFFFF
0.0010
INL EROR (%FSR)
0.0010 0.0005 0 -0.0005 -0.0010 -0.0015 AVDD = +15V AVSS = -15V 10V RANGE TA = 25C -16 -12 -8 -4 0 4 8 12 16 20
09226-036
09226-038 09226-037
0.0005 0 -0.0005 -0.0010 -0.0015
09226-034
0V TO 10V RANGE MAX INL 0V TO 10V RANGE MIN INL TA = 25C AVSS = -26.4V FOR AVDD > +26.4V
-0.0020
10
15
20 SUPPLY (V)
25
30
-0.0020 -20
OUTPUT CURRENT (mA)
Figure 20. Integral Nonlinearity Error vs. AVDD/|AVSS|
1.0 0.8 0.6 AVDD = +15V AVSS = -15V ALL RANGES TA = 25C AVSS = -26.4V FOR AVDD > +26.4V
12
Figure 23. Source and Sink Capability of Output Amplifier
AVDD = +15V AVSS = -15V 10V RANGE TA = 25C OUTPUT UNLOADED
8
DNL ERROR (%FSR)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 10
OUTPUT VOLTAGE (V)
09226-138
4
DNL ERROR MAX DNL ERROR MIN
0
-4
-8
15
20 SUPPLY (V)
25
30
-12 -5
0
5 TIME (s)
10
15
Figure 21. Differential Nonlinearity Error vs. AVDD/|AVSS|
0.008
12
Figure 24. Full-Scale Positive Step
AVDD = +15V AVSS = -15V 10V RANGE TA = 25C OUTPUT UNLOADED
TOTAL UNADJUSTED ERROR (%FSR)
0.006
0V TO 10V RANGE MAX INL 0V TO 10V RANGE MIN INL TA = 25C AVSS = -26.4V FOR AVDD > +26.4V
OUTPUT VOLTAGE (V)
09226-035
8
0.004
4
0.002
0
0
-4
-0.002
-8
-0.004 10
15
20 SUPPLY (V)
25
30
-12 -5
0
5 TIME (s)
10
15
Figure 22. Total Unadjusted Error vs. AVDD/|AVSS|
Figure 25. Full-Scale Negative Step
Rev. A | Page 17 of 48
AD5755-1
15 10 0x7FFF TO 0x8000 0x8000 TO 0x7FFF AVDD = +15V AVSS = -15V +10V RANGE TA = 25C
25 20 15
OUTPUT VOLTAGE (mV)
5 0 -5 -10 -15 -20
OUTPUT VOLTAGE (mV)
10 5 0 -5 -10 -15 -20 AVDD = +15V AVSS = -15V TA = 25C 0 25 50 TIME (s) 75 100 125
09226-043
09226-045
0
1
2 TIME (s)
3
4
5
09226-039
-25
Figure 26. Digital-to-Analog Glitch
15
Figure 29. VOUT_x vs. Time on Power-Up
60 40 20
10
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
AVDD = +15V AVSS = -15V 10V RANGE TA = 25C OUTPUT UNLOADED
5
0 -20 -40 -60 -80 -100 -120 POC = 1 POC = 0 AVDD = +15V AVSS = -15V 10V RANGE TA = 25C INT_ENABLE = 1 0 2 4 TIME (s) 6 8 10
09226-044
0
-5
-10
0
1
2
3
4
5 TIME (s)
6
7
8
9
10
Figure 27. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
300 AVDD = +15V AVSS = -15V 10V RANGE OUTPUT UNLOADED TA = 25C
09226-040
-15
-140
Figure 30. VOUT_x vs. Time on Output Enable
0 AVDD = +15V VBOOST = +15V AVSS = -15V TA = 25C
200
OUTPUT VOLTAGE (V)
-20
0
VOUT_x PSRR (dB)
09226-041
100
-40
-60
-100
-80
-200
-100
-300
0
1
2
3
4
5 TIME (s)
6
7
8
9
10
-120 10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 28. Peak-to-Peak Noise (100 kHz Bandwidth)
Figure 31. VOUT_x PSRR vs. Frequency
Rev. A | Page 18 of 48
AD5755-1
CURRENT OUTPUTS
0.0025 AVDD = +15V AVSS = -15V TA = 25C 0.0015
INL ERROR (%FSR)
INL ERROR (%FSR)
0.0010 0.0008 0.0006 0.0004 0.0002 0 -0.0002 -0.0004 -0.0006
09226-149
0.0005
-0.0005
4mA TO 0mA TO 0mA TO 0mA TO 4mA TO 0mA TO
20mA RANGE MAX INL 24mA RANGE MAX INL 20mA RANGE MIN INL 20mA RANGE MAX INL 20mA RANGE MAX INL 24mA RANGE MIN INL
AVDD = +15V AVSS = -15V/0V
-0.0015
-0.0008 -0.0010 -40 -20 0 20 40 60 80 100
-0.0025
0
10000
20000
30000 CODE
40000
50000
60000
TEMPERATURE (C)
Figure 32. Integral Nonlinearity vs. Code
1.0 0.8 0.6
DNL ERROR (LSB)
INL ERROR (%FSR)
Figure 35. Integral Nonlinearity vs. Temperature, Internal RSET
0.0020
AVDD = +15V AVSS = -15V TA = 25C
0.0015 0.0010 0.0005 0 -0.0005 -0.0010
4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MAX INL 0mA TO 20mA RANGE MIN INL
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0
09226-150
0mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL
10000
20000
30000 CODE
40000
50000
60000
-0.0020 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
Figure 33. Differential Nonlinearity vs. Code
0.035 0.030
TOTAL UNADJUSTED ERROR (%FSR)
Figure 36. Integral Nonlinearity vs. Temperature, External RSET
1.0 0.8 0.6
AVDD = +15V AVSS = -15V/0V ALL RANGES INTERNAL AND EXTERNAL R SET
0.025
DNL ERROR (%FSR)
0.020 0.015 0.010 0.005 0 -0.005
AVDD = +15V AVSS = -15V TA = 25C ALL CHANNELS ENABLED
4mA TO 4mA TO 4mA TO 4mA TO 20mA, 20mA, 20mA, 20mA, EXTERNAL R SET EXTERNAL R SET, WITH DC-TO-DC CONVERTER INTERNAL RSET INTERNAL RSET, WITH DC-TO-DC CONVERTER
0.4 0.2 0 -0.2 -0.4 -0.6
DNL ERROR MAX DNL ERROR MIN
09226-151
-0.010 -0.015 0 10000 20000 30000 CODE 40000 50000 60000
-0.8 -1.0 -40
-20 0 20 40 60 TEMPERATURE (C) 80 100
Figure 34. Total Unadjusted Error vs. Code
Figure 37. Differential Nonlinearity vs. Temperature
Rev. A | Page 19 of 48
09226-154
09226-153
4mA TO 4mA TO 4mA TO 4mA TO
20mA, 20mA, 20mA, 20mA,
EXTERNAL RSET EXTERNAL RSET, WITH DC-TO-DC CONVERTER INTERNAL RSET INTERNAL RSET, WITH DC-TO-DC CONVERTER
-0.0015
AVDD = +15V AVSS = -15V/0V
09226-152
4mA TO 4mA TO 4mA TO 4mA TO
20mA, 20mA, 20mA, 20mA,
EXTERNAL RSET EXTERNAL RSET, WITH DC-TO-DC CONVERTER INTERNAL RSET INTERNAL RSET, WITH DC-TO-DC CONVERTER
AD5755-1
0.03 0.02
TOTAL UNADJSUTED ERROR (%FSR)
0.02 0.01 0 GAIN ERROR (%FSR) -0.01 -0.02 -0.03 -0.04
09226-155
0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 -40
-20 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO 0 20mA INTERNAL R SET 20mA INTERNAL R SET 24mA INTERNAL R SET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET 80 100 AVDD = +15V AVSS = -15V/0V
AVDD = +15V AVSS = -15V/0V 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO -20 0 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET 80 100
20 40 60 TEMPERATURE (C)
-0.06 -40
20 40 60 TEMPERATURE (C)
Figure 38. Total Unadjusted Error vs. Temperature
0.03 0.02 0.01
FULL-SCALE ERROR (%FSR)
Figure 41. Gain Error vs. Temperature
0.0025 0.0020 0.0015
4mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL TA = 25C AVSS = -26.4V FOR AVDD > +26.4V
0
INL ERROR (%FSR)
-0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 -0.08 -40 -20 AVDD = +15V AVSS = -15V/0V 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO 0 20mA INTERNAL R SET 20mA INTERNAL R SET 24mA INTERNAL R SET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET 80 100
0.0010 0.0005 0 -0.0005 -0.0010
09226-157
-0.0015
20 40 60 TEMPERATURE (C)
15
20 SUPPLY (V)
25
30
Figure 39. Full Scale Error vs. Temperature
0.020 0.015 0.010
INL ERROR (%FSR)
Figure 42. Integral Nonlinearity Error vs. AVDD/|AVSS|, Over Supply, External RSET
0.0015 0.0010 0.0005 0 -0.0005 -0.0010 -0.0015
09226-158
OFFSET ERROR (%FSR)
0.005 0 -0.005 -0.010 -0.015 -0.020 -40
AVDD = +15V AVSS = -15V/0V 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO -20 0 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL R SET 20mA EXTERNAL R SET 24mA EXTERNAL R SET 80 100
-0.0020 -0.0025 10
4mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL TA = 25C AVSS = -26.4V FOR AVDD > +26.4V 15 20 SUPPLY (V) 25 30
09226-057
20 40 60 TEMPERATURE (C)
Figure 40. Offset Error vs. Temperature
Figure 43. Integral Nonlinearity Error vs. AVDD/|AVSS|, Over Supply, Internal RSET
Rev. A | Page 20 of 48
09226-056
-0.0020 10
09226-159
-0.05
AD5755-1
1.0 0.8 0.6
DNL ERROR (%FSR)
6
ALL RANGES INTERNAL AND EXTERNAL R SET TA = 25C AVSS = -26.4V FOR AVDD > +26.4V
5
AVDD = +15V AVSS = -15V TA = 25C RLOAD = 300
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 10
15 20 SUPPLY (V) 25 30
09226-162
DNL ERROR MAX DNL ERROR MIN
CURRENT (A)
4
3
2
1
0
5
10 TIME (s)
15
20
Figure 44. Differential Nonlinearity Error vs. AVDD
0.012
Figure 47. Output Current vs. Time on Power-Up
4 2 0
CURRENT (A)
TOTAL UNADJUSTED ERROR (%FSR)
0.010
0.008
-2 -4 -6 -8 -10
0.006
0.004 4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE TA = 25C AVSS = -26.4V FOR AVDD > +26.4V 15 20 SUPPLY (V) 25 30
09226-060
0.002
AVDD = +15V AVSS = -15V TA = 25C RLOAD = 300 INT_EN = 1 0 1 2 3 TIME (s) 4 5 6
09226-063
0 10
Figure 45. Total Unadjusted Error vs. AVDD, External RSET
0 -0.002
30
Figure 48. Output Current vs. Time on Output Enable
TOTAL UNADJUSTED ERROR (%FSR)
-0.004 -0.006 -0.008 -0.010 -0.012 -0.014 -0.016 -0.018
09226-061
25
OUTPUT CURRENT (mA)
4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE TA = 25C AVSS = -26.4V FOR AVDD > +26.4V
20
15
IOUT VBOOST 0mA TO 24mA RANGE 1k LOAD fSW = 410kHz INDUCTOR = 10H (XAL4040-103) AVCC = 5V TA = 25C 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
10
5
-0.020 10
15
20 SUPPLY (V)
25
30
0 -0.50 -0.25
TIME (ms)
Figure 46. Total Unadjusted Error vs. AVDD, Internal RSET
Figure 49. Output Current and VBOOST_x Settling Time with DC-to-DC Converter (See Figure 80)
Rev. A | Page 21 of 48
09226-167
09226-062
0
AD5755-1
30
8 7
HEADROOM VOLTAGE (V)
25
OUTPUT CURRENT (mA)
6 5 4 3 2 1
0mA TO 24mA RANGE 1k LOAD FSW = 410kHz INDUCTOR = 10H (XAL4040-103) TA = 25C
20
15
IOUT, TA = -40C IOUT, TA = +25C IOUT, TA = +105C 0mA TO 24mA RANGE 1k LOAD fSW = 410kHz INDUCTOR = 10H (XAL4040-103) AVCC = 5V 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75
10
5
0
5
10 CURRENT (mA)
15
20
TIME (ms)
Figure 50. Output Current Settling with DC-to-DC Converter vs. Time and Temperature (See Figure 80)
30
Figure 53. DC-to-DC Converter Headroom vs. Output Current (See Figure 80)
0 AVDD = +15V VBOOST = +15V AVSS = -15V TA = 25C
25
OUTPUT CURRENT (mA)
-20
15
IOUT, AVCC = 4.5V IOUT, AVCC = 5.0V IOUT, AVCC = 5.5V 0mA TO 24mA RANGE 1k LOAD fSW = 410kHz INDUCTOR = 10H (XAL4040-103) TA = 25C 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75
IOUT_x PSRR (dB)
20
-40
-60
10
-80
5
-100
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100
1k
10k
100k
1M
10M
TIME (ms)
FREQUENCY (Hz)
Figure 51. Output Current Settling with DC-to-DC Converter vs. Time and AVCC (See Figure 80)
10 8
20mA OUTPUT 10mA OUTPUT
Figure 54. IOUT_x PSRR vs. Frequency
CURRENT (AC COUPLED) (A)
6 4 2 0 -2 -4 -6 -8 -10 0 2
AVCC = 5V fSW = 410kHz INDUCTOR = 10H (XAL4040-103)
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0mA TO 24mA RANGE 1k LOAD EXTERNAL R SET TA = 25C
4
6
8 TIME (s)
10
12
14
Figure 52. Output Current vs. Time with DC-to-DC Converter (See Figure 80)
Rev. A | Page 22 of 48
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0 -0.25
-120 10
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0 -0.25
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0
AD5755-1
DC-TO-DC BLOCK
90 85
VBOOST_x EFFICIENCY (%)
80
AVCC = 4.5V AVCC = 5V AVCC = 5.5V
IOUT_x EFFICIENCY (%)
20mA 70
80 75 70 65 60 55 50 0mA TO 24mA RANGE 1k LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10H (XAL4040-103) TA = 25C
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60
50
40
30
0mA TO 24mA RANGE 1k LOAD EXTERNAL RSET AVCC = 5V fSW = 410 kHz INDUCTOR = 10H (XAL4040-103) -20 0 20 40 60 80 100
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0
4
8
12 CURRENT (mA)
16
20
24
20 -40
TEMPERATURE (C)
Figure 55. Efficiency at VBOOST_x vs. Output Current (See Figure 80)
90 20mA 85
VBOOST_x EFFICIENCY (%)
Figure 58. Output Efficiency vs. Temperature (See Figure 80)
0.6
0.5
SWITCH RESISTANCE ()
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80 75 70 65 60 55 50 -40 0mA TO 24mA RANGE 1k LOAD EXTERNAL RSET AVCC = 5V fSW = 410kHz INDUCTOR = 10H (XAL4040-103)
0.4
0.3
0.2
0.1
-20
0
20
40
60
80
100
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
Figure 56. Efficiency at VBOOST_x vs. Temperature (See Figure 80)
80 AVCC = 4.5V AVCC = 5V AVCC = 5.5V
Figure 59. Switch Resistance vs. Temperature
70
IOUT_x EFFICIENCY (%)
60
50
40
30
0mA TO 24mA RANGE 1k LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10H (XAL4040-103) TA = 25C 0 4 8 12 CURRENT (mA) 16 20 24
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20
Figure 57. Output Efficiency vs. Output Current (See Figure 80)
Rev. A | Page 23 of 48
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0 -40
AD5755-1
REFERENCE
16 14 12 10 AVDD REFOUT TA = 25C
5.0050 5.0045 5.0040 5.0035
REFOUT (V)
30 DEVICES SHOWN AVDD = 15V
VOLTAGE (V)
8 6 4 2 0
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5.0030 5.0025 5.0020 5.0015 5.0010 5.0005
0
0.2
0.4
0.6 TIME (ms)
0.8
1.0
1.2
-20
0
20
40
60
80
100
TEMPERATURE (C)
Figure 60. REFOUT Turn-On Transient
Figure 63. REFOUT vs. Temperature (When the AD5755-1 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is -4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. This second shift is due to the relaxation of stress incurred during soldering.)
5.002
4 3 2 AVDD = 15V TA = 25C
5.001 5.000
AVDD = 15V TA = 25C
REFOUT (V)
1 0 -1 -2 -3
REFOUT (V)
4.999 4.998 4.997 4.996 4.995
0
2
4 TIME (s)
6
8
10
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0
2
4
6
8
10
LOAD CURRENT (mA)
Figure 61. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)
150 AVDD = 15V TA = 25C 100
Figure 64. REFOUT vs. Load Current
5.00000 4.99995 4.99990 TA = 25C
REFOUT (V)
50
0
REFOUT (V)
4.99985 4.99980 4.99975 4.99970
-50
-100
4.99965
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0
5
10 TIME (ms)
15
20
15
20 AVDD (V)
25
30
Figure 62. REFOUT Output Noise (100 kHz Bandwidth)
Figure 65. REFOUT vs. Supply
Rev. A | Page 24 of 48
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-150
4.99960 10
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-2
5.0000 -40
AD5755-1
GENERAL
450 400 350 DVCC = 5V TA = 25C
13.4 13.3 13.2
FREQUENCY (MHz)
300
DICC (A)
13.1 13.0 12.9 12.8 12.7 DVCC = 5.5V
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250 200 150 100 50
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0
0
1
2
3
4
5
12.6 -40
-20
0
20
40
60
80
100
SDIN VOLTAGE (V)
TEMPERATURE (C)
Figure 66. DICC vs. Logic Input Voltage
10 8 6 4 AIDD AISS TA = 25C VOUT = 0V OUTPUT UNLOADED
Figure 69. Internal Oscillator Frequency vs. Temperature
14.4 14.2 14.0
CURRENT (mA)
2 0 -2 -4 -6 -8 -10
FREQUENCY (MHz)
13.8 13.6 13.4 13.2 13.0 2.5
DVCC = 5.5V TA = 25C 3.0 3.5 4.0 VOLTAGE (V) 4.5 5.0 5.5
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15
20 VOLTAGE (V)
25
30
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-12 10
Figure 67. AIDD/AISS vs. AVDD/|AVSS|
8 7 6
CURRENT (mA)
Figure 70. Internal Oscillator Frequency vs. DVCC Supply Voltage
5 4 3 2 1 0 10 AIDD TA = 25C IOUT = 0mA 15 20 VOLTAGE (V) 25 30
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Figure 68. AIDD vs. AVDD
Rev. A | Page 25 of 48
AD5755-1 TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in LSBs, from the best fit line through the DAC transfer function. A typical INL vs. code plot is shown in Figure 8. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot is shown in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5755-1 is monotonic over its full operating temperature range. Negative Full-Scale Error/Zero-Scale Error Negative full-scale error is the error in the DAC output voltage when 0x0000 (straight binary coding) is loaded to the DAC register. Zero-Scale TC This is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/C. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (straight binary coding). Bipolar Zero TC Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/C. Offset Error In voltage output mode, offset error is the deviation of the analog output from the ideal quarter-scale output when in bipolar output ranges and the DAC register is loaded with 0x4000 (straight binary coding). In current output mode, offset error is the deviation of the analog output from the ideal zero-scale output when all DAC registers are loaded with 0x0000. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed in % FSR. Gain TC This is a measure of the change in gain error with changes in temperature. Gain TC is expressed in ppm FSR/C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be full-scale - 1 LSB. Full-scale error is expressed in percent of full-scale range (% FSR). Full-Scale TC Full-scale TC is a measure of the change in full-scale error with changes in temperature and is expressed in ppm FSR/C. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error taking all the various errors into account, including INL error, offset error, gain error, temperature, and time. TUE is expressed in % FSR. DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC, which is at midscale. Current Loop Compliance Voltage The maximum voltage at the IOUT_x pin for which the output current is equal to the programmed value. Voltage Reference Thermal Hysteresis Voltage reference thermal hysteresis is the difference in output voltage measured at +25C compared to the output voltage measured at +25C after cycling the temperature from +25C to -40C to +105C and back to +25C. The hysteresis is specified for the first and second temperature cycles and is expressed in ppm. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. A plot of settling time is shown in Figure 24, Figure 50, and Figure 51. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltageoutput digital-to-analog converter is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in V/s. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5755-1 is powered-on. It is specified as the area of the glitch in nV-sec. See Figure 29 and Figure 47. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state, but the output voltage remains constant. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000). See Figure 26.
Rev. A | Page 26 of 48
AD5755-1
Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000). See Figure 26. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and a subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Reference TC Reference TC is a measure of the change in the reference output voltage with a change in temperature. It is expressed in ppm/C. Line Regulation Line regulation is the change in reference output voltage due to a specified change in supply voltage. It is expressed in ppm/V. Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA. DC-to-DC Converter Headroom This is the difference between the voltage required at the current output and the voltage supplied by the dc-to-dc converter. See Figure 53. Output Efficiency I 2 x R LOAD OUT
AVCC x AI CC
This is defined as the power delivered to a channel's load vs. the power delivered to the channel's dc-to-dc input. Efficiency at VBOOST_x I OUT x V BOOST _ x
AVCC x AI CC
This is defined as the power delivered to a channel's VBOOST_x supply vs. the power delivered to the channel's dc-to-dc input. The VBOOST_x quiescent current is considered part of the dc-todc converter's losses.
Rev. A | Page 27 of 48
AD5755-1 THEORY OF OPERATION
The AD5755-1 is a quad, precision digital-to-current loop and voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop and unipolar/bipolar voltage outputs. The current ranges available are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The voltage ranges available are 0 V to 5 V, 5 V, 0 V to 10 V, and 10 V. The current and voltage outputs are available on separate pins, and only one is active at any one time. The desired output configuration is user selectable via the DAC control register. On-chip dynamic power control minimizes package power dissipation in current mode.
VBOOST_x R2 T2 A2 16-BIT DAC T1 A1 IOUT_x R3
Figure 73. Voltage-to-Current Conversion Circuitry
Voltage Output Amplifier
The voltage output amplifier is capable of generating both unipolar and bipolar output voltages. It is capable of driving a load of 1 k in parallel with 1 F (with an external compensation capacitor) to AGND. The source and sink capabilities of the output amplifier are shown in Figure 23. The slew rate is 1.9 V/s with a full-scale settling time of 16 s (10 V step). If remote sensing of the load is not required, connect +VSENSE_x directly to VOUT_x. + VSENSE_x must stay within 3.0 V of VOUT_x for correct operation.
DAC ARCHITECTURE
The DAC core architecture of the AD5755-1 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 71. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either ground or the reference buffer output. The remaining 12 bits of the data-word drive Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder network.
VOUT 2R 2R S0 2R S1 2R S11 2R E1 2R E2 2R E15
Driving Large Capacitive Loads
The voltage output amplifier is capable of driving capacitive loads of up to 2 F with the addition of a 220 pF nonpolarized compensation capacitor on each channel. Care should be taken to choose an appropriate value of compensation capacitor. This capacitor, while allowing the AD5755-1 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and, therefore, affects the bandwidth of the system. Without the compensation capacitor, up to 10 nF capacitive loads can be driven. See Table 5 for information on connecting compensation capacitors.
8-/12-BIT R-2R LADDER
FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS
Figure 71. DAC Ladder Structure
The voltage output from the DAC core is either converted to a current (see Figure 73), which is then mirrored to the supply rail so that the application simply sees a current source output, or it is buffered and scaled to output a software selectable unipolar or bipolar voltage range (see Figure 72). Both the voltage and current outputs are supplied by VBOOST_x. The current and voltage are output on separate pins and cannot be output simultaneously. A channel's current and voltage output pins can be tied together.
+VSENSE_x RANGE SCALING
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Reference Buffers
The AD5755-1 can operate with either an external or internal reference. The reference input requires a 5 V reference for specified performance. This input voltage is then buffered before it is applied to the DAC.
POWER-ON STATE OF THE AD5755-1
On initial power-up of the AD5755-1, the power-on reset circuit powers up in a state that is dependent on the power-on condition (POC) pin. If POC = 0, the voltage output and current output channels power up in tristate mode. If POC = 1, the voltage output channel powers up with a 30 k pull-down resistor to ground, and the current output channel powers up to tristate. Even though the output ranges are not enabled, the default output range is 0 V to 5 V, and the clear code register is loaded
Rev. A | Page 28 of 48
DAC
VOUT_x
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VOUT_X SHORT FAULT
Figure 72. Voltage Output
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RSET
AD5755-1
with all zeros. This means that if the user clears the part after power-up, the output is actively driven to 0 V (if the channel has been enabled for clear).
OUTPUT I/V AMPLIFIER VREFIN 16-BIT DAC VOUT_x
SERIAL INTERFACE
The AD5755-1 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP standards. Data coding is always straight binary.
LDAC DAC REGISTER
DAC INPUT REGISTER OFFSET AND GAIN CALIBRATION DAC DATA REGISTER
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If packet error checking, or PEC (see the Device Features section), is enabled, an additional eight bits must be written to the AD5755-1, creating a 32-bit serial interface. There are two ways in which the DAC outputs can be updated: individual updating or simultaneous updating of all DACs.
SCLK SYNC SDIN
SDO
Figure 74. Simplified Serial Interface of Input Loading Circuitry for One DAC Channel
TRANSFER FUNCTION
Table 6 shows the input code to ideal output voltage relationship for the AD5755-1 for straight binary data coding of the 10 V output range. Table 6. Ideal Output Voltage to Input Code Relationship
Digital Input Straight Binary Data Coding MSB LSB 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 Analog Output VOUT +2 VREF x (32,767/32,768) +2 VREF x (32,766/32,768) 0V -2 VREF x (32,767/32,768) -2 VREF
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into the DAC data register. The addressed DAC output is updated on the rising edge of SYNC. See Table 3 and Figure 3 for timing information.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked into the DAC data register. Only the first write to each channel's DAC data register is valid after LDAC is brought high. Any subsequent writes while LDAC is still held high are ignored, though they are loaded into the DAC data register. All the DAC outputs are updated by taking LDAC low after SYNC is taken high.
Rev. A | Page 29 of 48
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INTERFACE LOGIC
AD5755-1 REGISTERS
Table 7 shows an overview of the registers for the AD5755-1. Table 7. Data, Control, and Readback Registers for the AD5755-1
Register Data DAC Data Register (x4) Gain Register (x4) Offset Register (x4) Clear Code Register (x4) Control Main Control Register Description Used to write a DAC code to each DAC channel. AD5755-1 data bits = D15 to D0. There are four DAC data registers, one per DAC channel. Used to program gain trim, on a per channel basis. AD5755-1 data bits = D15 to D0. There are four gain registers, one per DAC channel. Used to program offset trim, on a per channel basis. AD5755-1 data bits = D15 to D0. There are four offset registers, one per DAC channel. Used to program clear code on a per channel basis. AD5755-1 data bits = D15 to D0. There are four clear code registers, one per DAC channel. Used to configure the part for main operation. Sets functions such as status readback during write, enables output on all channels simultaneously, powers on all dc-to-dc converter blocks simultaneously, and enables and sets conditions of the watchdog timer. See the Device Features section for more details. Has three functions. Used to perform a reset, to toggle the user bit, and, as part of the watchdog timer feature, to verify correct data communication operation. Used to program the slew rate of the output. There are four slew rate control registers, one per channel. These registers are used to control the following: Set the output range, for example, 4 mA to 20 mA, 0 V to 10 V. Set whether an internal/external sense resistor is used. Enable/disable a channel for CLEAR. Enable/disable overrange. Enable/disable internal circuitry on a per channel basis. Enable/disable output on a per channel basis. Power on dc-to-dc converters on a per channel basis. There are four DAC control registers, one per DAC channel. Use to set the dc-to-dc control parameters. Can control dc-to-dc maximum voltage, phase, and frequency. This contains any fault information, as well as a user toggle bit.
Software Register Slew Rate Control Register (x4) DAC Control Register (x4)
DC-to-DC Control Register Readback Status Register
Rev. A | Page 30 of 48
AD5755-1
PROGRAMMING SEQUENCE TO WRITE/ENABLE THE OUTPUT CORRECTLY
To correctly write to and set up the part from a power-on condition, use the following sequence: 1. 2. Perform a hardware or software reset after initial power-on. The dc-to-dc converter supply block must be configured. Set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at. Configure the DAC control register on a per channel basis. The output range is selected, and the dc-to-dc converter block is enabled (DC_DC bit). Other control bits can be configured at this point. Set the INT_ENABLE bit; however, the output enable bit (OUTEN) should not be set. Write the required code to the DAC data register. This implements a full DAC calibration internally. Allow at least 200 s before Step 5 for reduced output glitch. Write to the DAC control register again to enable the output (set the OUTEN bit).
CHANGING AND REPROGRAMMING THE RANGE
When changing between ranges, the same sequence as described in the Programming Sequence to Write/Enable the Output Correctly section should be used. It is recommended to set the range to its zero point (can be midscale or zero scale) prior to disabling the output. Because the dc-to-dc switching frequency, maximum voltage, and phase have already been selected, there is no need to reprogram these. A flowchart of this sequence is shown in Figure 76.
CHANNEL'S OUTPUT IS ENABLED.
3.
STEP 1: WRITE TO CHANNEL'S DAC DATA REGISTER. SET THE OUTPUT TO 0V (ZERO OR MIDSCALE).
4.
STEP 2: WRITE TO DAC CONTROL REGISTER. DISABLE THE OUTPUT (OUTEN = 0), AND SET THE NEW OUTPUT RANGE. KEEP THE DC_DC BIT AND THE INT_ENABLE BIT SET.
5.
STEP 3: WRITE VALUE TO THE DAC DATA REGISTER.
A flowchart of this sequence is shown in Figure 75.
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POWER ON.
STEP 4: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 2 ABOVE. THIS TIME SELECT THE OUTEN BIT TO ENABLE THE OUTPUT.
STEP 1: PERFORM A SOFTWARE/HARDWARE RESET.
Figure 76. Steps for Changing the Output Range
STEP 2: WRITE TO DC-TO-DC CONTROL REGISTER TO SET DC-TO-DC CLOCK FREQUENCY, PHASE, AND MAXIMUM VOLTAGE.
STEP 3: WRITE TO DAC CONTROL REGISTER. SELECT THE DAC CHANNEL AND OUTPUT RANGE. SET THE DC_DC BIT AND OTHER CONTROL BITS AS REQUIRED. SET THE INT_ENABLE BIT BUT DO NOT SELECT THE OUTEN BIT.
STEP 4: WRITE TO EACH/ALL DAC DATA REGISTERS. ALLOW AT LEAST 200s BETWEEN STEP 3 AND STEP 5 FOR REDUCED OUTPUT GLITCH.
Figure 75. Programming Sequence for Enabling the Output Correctly
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STEP 5: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 3 ABOVE. THIS TIME SELECT THE OUTEN BIT TO ENABLE THE OUTPUT.
Rev. A | Page 31 of 48
AD5755-1
DATA REGISTERS
The input register is 24 bits wide. When PEC is enabled, the input register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information on PEC). When writing to a data register, the format in Table 8 must be used.
DAC Data Register
When writing to the AD5755-1 DAC data registers, D15 to D0 are used for DAC data bits. Table 10 shows the register format and Table 9 describes the function of Bit D23 to Bit D16.
Table 8. Writing to a Data Register
MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 DREG2 D19 DREG1 D18 DREG0 D17 DAC_AD1 D16 DAC_AD0 LSB D15 to D0 Data
Table 9. Input Register Decode
Bit R/W DUT_AD1, DUT_AD0 Description Indicates a read from or a write to the addressed register. Used in association with the external pins, AD1 and AD0, to determine which AD5755-1 device is being addressed by the system controller. DUT_AD1 DUT_AD0 Function 0 0 Addresses part with Pin AD1 = 0, Pin AD0 = 0 0 1 Addresses part with Pin AD1 = 0, Pin AD0 = 1 1 0 Addresses part with Pin AD1 = 1, Pin AD0 = 0 1 1 Addresses part with Pin AD1 = 1, Pin AD0 = 1 Selects whether a data register or a control register is written to. If a control register is selected, a further decode of CREG bits (see Table 17) is required to select the particular control register, as follows. DREG2 DREG1 DREG0 Function 0 0 0 1 1 1 1 DAC_AD1, DAC_AD0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 Write to DAC data register (individual channel write) Write to gain register Write to gain register (all DACs) Write to offset register Write to offset register (all DACs) Write to clear code register Write to a control register
DREG2, DREG1, DREG0
These bits are used to decode the DAC channel. DAC_AD1 DAC_AD0 DAC Channel/Register Address 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D X X These are don't cares if they are not relevant to the operation being performed.
Table 10. Programming the DAC Data Registers
MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 DREG2 D19 DREG1 D18 DREG0 D17 DAC_AD1 D16 DAC_AD0 LSB D15 to D0 DAC data
Rev. A | Page 32 of 48
AD5755-1
Gain Register
The 16-bit gain register, as shown in Table 11, allows the user to adjust the gain of each channel in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 010. It is possible to write the same gain code to all four DAC channels at the same time by setting the DREG[2:0] bits to 011. The gain register coding is straight binary as shown in Table 12. The default code in the gain register is 0xFFFF. In theory, the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is about 50% of programmed range to maintain accuracy. See the Digital Offset and Gain Control section for more information. in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 100. It is possible to write the same offset code to all four DAC channels at the same time by setting the DREG[2:0] bits to 101. The offset register coding is straight binary as shown in Table 14. The default code in the offset register is 0x8000, which results in zero offset programmed to the output. See the Digital Offset and Gain Control section for more information.
Clear Code Register
The 16-bit clear code register allows the user to set the clear value of each channel as shown in Table 15. It is possible, via software, to enable or disable on a per channel basis which channels are cleared when the CLEAR pin is activated. The default clear code is 0x0000. See the Asynchronous Clear section for more information.
Offset Register
The 16-bit offset register, as shown in Table 13, allows the user to adjust the offset of each channel by -32,768 LSBs to +32,767 LSBs Table 11. Programming the Gain Register
R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 0 DREG1 1
DREG0 0
DAC_AD1 DAC_AD0 DAC channel address
D15 to D0 Gain adjustment
Table 12. Gain Register
Gain Adjustment +65,535 LSBs +65,534 LSBs ... 1 LSB 0 LSBs R/W 0 DUT_AD1 DUT_AD0 Device address G15 1 1 ... 0 0 DREG2 1 G14 1 1 ... 0 0 DREG1 0 G13 1 1 ... 0 0 DREG0 0 G12 to G4 1 1 ... 0 0 G3 1 1 ... 0 0 G2 1 1 ... 0 0 G1 1 0 ... 0 0 G0 1 0 ... 1 0
Table 13. Programming the Offset Register
DAC_AD1 DAC_AD0 DAC channel address D15 to D0 Offset adjustment
Table 14. Offset Register Options
Offset Adjustment +32,767 LSBs +32,766 LSBs ... No Adjustment (Default) ... -32,767 LSBs -32,768 LSBs R/W 0 OF15 1 1 ... 1 ... 0 0 OF14 1 1 ... 0 ... 0 0 DREG2 1 OF13 1 1 ... 0 ... 0 0 DREG1 1 OF12 to OF4 1 1 ... 0 ... 0 0 DREG0 0 OF3 1 1 ... 0 ... 0 0 OF2 1 1 ... 0 ... 0 0 OF1 1 0 ... 0 ... 0 0 OF0 1 0 ... 0 ... 0 0
Table 15. Programming the Clear Code Register
DUT_AD1 DUT_AD0 Device address DAC_AD1 DAC_AD0 DAC channel address D15 to D0 Clear code
Rev. A | Page 33 of 48
AD5755-1
CONTROL REGISTERS
When writing to a control register, the format shown in Table 16 must be used. See Table 9 for information on the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits to the appropriate decode address for that register, according to Table 17. These CREG bits select among the various control registers.
Main Control Register
The main control register options are shown in Table 18 and Table 19. See the Device Features section for more information on the features controlled by the main control register.
Table 16. Writing to a Control Register
MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 1 D19 1 D18 1 D17 DAC_AD1 D16 DAC_AD0 D15 CREG2 D14 CREG1 D13 CREG0 LSB D12 to D0 Data
Table 17. Register Access Decode
CREG2 (D15) 0 0 0 0 1 CREG1 (D14) 0 0 1 1 0 CREG0 (D13) 0 1 0 1 0 Function Slew rate control register (one per channel) Main control register DAC control register (one per channel) DC-to-dc control register Software register (one per channel)
Table 18. Programming the Main Control Register
MSB D15 0
1
D14 0
D13 1
D12 POC
D11 STATREAD
D10 EWD
D9 WD1
D8 WD0
D7 X1
D6 ShtCctLim
D5 OUTEN_ALL
D4 DCDC_ALL
LSB D3 to D0 X1
X = don't care.
Table 19. Main Control Register Functions
Bit POC Description The POC bit determines the state of the voltage output channels during normal operation. Its default value is 0. POC = 0. The output goes to the value set by the POC hardware pin when the voltage output is not enabled (default). POC = 1. The output goes to the opposite value of the POC hardware pin if the voltage output is not enabled. Enable status readback during a write. See the Device Features section. STATREAD = 1, enable. STATREAD = 0, disable (default). Enable watchdog timer. See the Device Features section for more information. EWD = 1, enable watchdog. EWD = 0, disable watchdog (default). Timeout select bits. Used to select the timeout period for the watchdog timer. WD1 WD0 Timeout Period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 Programmable short-circuit limit on the VOUT_x pin in the event of a short-circuit condition. 0 = 16 mA (default). 1 = 8 mA. Enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register. When set, powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register.
Rev. A | Page 34 of 48
STATREAD
EWD
WD1, WD0
ShtCctLim
OUTEN_ALL DCDC_ALL
AD5755-1
DAC Control Register
The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 20 and Table 21. Table 20. Programming DAC Control Register
D15 0
1
D14 1
D13 0
D12 X1
D11 X1
D10 X1
D9 X1
D8 INT_ENABLE
D7 CLR_EN
D6 OUTEN
D5 RSET
D4 DC_DC
D3 OVRNG
D2 R2
D1 R1
D0 R0
X = don't care.
Table 21. DAC Control Register Functions
Bit INT_ENABLE Description Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. Does not enable the output. Can only be done on a per channel basis. It is recommended to set this bit and allow a >200 s delay before enabling the output because this results in a reduced output enable glitch. See Figure 30 and Figure 48 for plots of this glitch. Per channel clear enable bit. Selects if this channel clears when the CLEAR pin is activated. CLR_EN = 1, channel clears when the part is cleared. CLR_EN = 0, channel does not clear when the part is cleared (default). Enables/disables the selected output channel. OUTEN = 1, enables the channel. OUTEN = 0, disables the channel (default). Selects an internal or external current sense resistor for the selected DAC channel. RSET = 0, selects the external resistor (default). RSET = 1, selects the internal resistor. Powers the dc-to-dc converter on the selected channel. DC_DC = 1, power up the dc-to-dc converter. DC_DC = 0, power down the dc-to-dc converter (default). This allows per channel dc-to-dc converter power-up/power-down. To power down the dc-to-dc converter, the OUTEN and INT_ENABLE bits must also be set to 0. All dc-to-dc converters can also be powered up simultaneously using the DCDC_ALL bit in the main control register. Enables 20% overrange on voltage output channel only. No current output overrange available. OVRNG = 1, enabled. OVRNG = 0, disabled (default). Selects the output range to be enabled. R2 R1 R0 Output Range Selected 0 0 0 0 V to 5 V voltage range (default). 0 0 1 0 V to 10 V voltage range. 0 1 0 5 V voltage range. 0 1 1 10 V voltage range. 1 0 0 4 mA to 20 mA current range. 1 0 1 0 mA to 20 mA current range. 1 1 0 0 mA to 24 mA current range.
CLR_EN
OUTEN
RSET
DC_DC
OVRNG
R2, R1, R0
Rev. A | Page 35 of 48
AD5755-1
Software Register
The software register has three functions. It allows the user to perform a software reset to the part. It can be used to set the user toggle bit, D11, in the status register. It is also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication has not been lost between the MCU and the AD5755-1 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC). When the watchdog feature is enabled, the user must write 0x195 to the software register within the timeout period. If this command is not received within the timeout period, the ALERT pin signals a fault condition. This is only required when the watchdog timer function is enabled.
DC-to-DC Control Register
The dc-to-dc control register allows the user control over the dc-to-dc switching frequency and phase, as well as the maximum allowable dc-to-dc output voltage. The dc-to-dc control register options are shown in Table 24 and Table 25.
Table 22. Programming the Software Register
MSB D15 1 D14 0 D13 0 D12 User program LSB D11 to D0 Reset code/SPI code
Table 23. Software Register Functions
Bit User Program Description This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is set to 1. Likewise, when D12 is set to 0, Bit D11 of the status register is also set to zero. This feature can be used to ensure that the SPI pins are working correctly by writing a known bit value to this register and reading back the corresponding bit from the status register. Option Description Reset code Writing 0x555 to D[11:0] performs a reset of the AD5755-1. SPI code If the watchdog timer feature is enabled, 0x195 must be written to the software register (D11 to D0) within the programmed timeout period.
Reset Code/SPI Code
Table 24. Programming the DC-to-DC Control Register
MSB D15 0
1
D14 1
D13 1
D12 to D7 X1
D6 DC-DC Comp
D5 to D4 DC-DC phase
D3 to D2 DC-DC Freq
LSB D1 to D0 DC-DC MaxV
X = don't care.
Table 25. DC-to-DC Control Register Options
Bit DC-DC Comp Description Selects between an internal and external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements--Slewing sections in the Device Features section for more information. 0 = selects the internal 150 k compensation resistor (default). 1 = bypasses the internal compensation resistor for the dc-to-dc converter. In this mode, an external dc-to-dc compensation resistor must be used; this is placed at the COMPDCDC_x pin in series with the 10 nF dc-to-dc compensation capacitor to ground. Typically, a ~50 k resistor is recommended. User programmable dc-to-dc converter phase (between channels). 00 = all dc-to-dc converters clock on the same edge (default). 01 = Channel A and Channel B clock on the same edge, Channel C and Channel D clock on opposite edges. 10 = Channel A and Channel C clock on the same edge, Channel B and Channel D clock on opposite edges. 11 = Channel A, Channel B, Channel C, and Channel D clock 90 out of phase from each other. DC-to-dc switching frequency; these are divided down from the internal 13 MHz oscillator (see Figure 69 and Figure 70). 00 = 250 10% kHz. 01 = 410 10% kHz (default). 10 = 650 10% kHz. Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter. 00 = 23 V + 1 V/-1.5 V (default). 01 = 24.5 V 1 V. 10 = 27 V 1 V. 11 = 29.5 V 1V.
Rev. A | Page 36 of 48
DC-DC Phase
DC-DC Freq
DC-DC MaxV
AD5755-1
Slew Rate Control Register
This register is used to program the slew rate control for the selected DAC channel. This feature is available on both the current and voltage outputs. The slew rate control is enabled/ disabled and programmed on a per channel basis. See Table 26 and the Digital Slew Rate Control section for more information. addressed register. This second SPI transfer should either be a request to read yet another register on a third data transfer or 0x1CE000, which is the no operation command.
Readback Example
To read back the gain register of Device 1, Channel A on the AD5755-1, implement the following sequence: 1. Write 0xA80000 to the AD5755-1 input register. This configures the AD5755-1 Device Address 1 for read mode with the gain register of Channel A selected. All the data bits, D15 to D0, are don't cares. Follow with another read command or a no operation command (0x1CE000). During this command, the data from the Channel A gain register is clocked out on the SDO line.
READBACK OPERATION
Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. See Table 27 for the bits associated with a readback operation. The DUT_AD1 and DUT_AD0 bits, in association with Bits RD[4:0], select the register to be read. The remaining data bits in the write sequence are don't cares. During the next SPI transfer (see Figure 4), the data appearing on the SDO output contains the data from the previously Table 26. Programming the Slew Rate Control Register
D15 0
1
2.
D14 0
D13 0
D12 SE
D11 to D7 X1
D6 to D3 SR_CLOCK
D2 to D0 SR_STEP
X = don't care.
Table 27. Input Shift Register Contents for a Read Operation
D23 R/W
1
D22 DUT_AD1
D21 DUT_AD0
D20 RD4
D19 RD3
D18 RD2
D17 RD1
D16 RD0
D15 to D0 X1
X = don't care.
Table 28. Read Address Decoding
RD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 RD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 RD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 RD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 RD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Function Read DAC A data register Read DAC B data register Read DAC C data register Read DAC D data register Read DAC A control register Read DAC B control register Read DAC C control register Read DAC D control register Read DAC A gain register Read DAC B gain register Read DAC C gain register Read DAC D gain register Read DACA offset register Read DAC B offset register Read DAC C offset register Read DAC D offset register Clear DAC A code register Clear DAC B code register Clear DAC C code register Clear DAC D code register DAC A slew rate control register DAC B slew rate control register DAC C slew rate control register DAC D slew rate control register Read status register Read main control register Read dc-to-dc control register
Rev. A | Page 37 of 48
AD5755-1
Status Register
The status register is a read only register. This register contains any fault information as a well as a ramp active bit and a user toggle bit. When the STATREAD bit in the main control register is set, the status register contents can be read back on Table 29. Decoding the Status Register
MSB D15 DCDCD D14 DCDCC D13 DCDCB D12 DCDCA D11 User toggle D10 PEC error D9 Ramp active D8 Over TEMP D7 VOUT_D fault D6 VOUT_C fault D5 VOUT_B fault D4 VOUT_A fault D3 IOUT_D fault D2 IOUT_C fault D1 IOUT_B fault LSB D0 IOUT_A fault
the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation.
Table 30. Status Register Options
Bit DC-DCD Description In current output mode, this bit is set on Channel D if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX voltage). In this case, the IOUT_D fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information on this bit's operation under this condition. In voltage output mode, this bit is set if, on Channel D, the dc-to-dc converter is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. In current output mode, this bit is set on Channel C if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX voltage). In this case, the IOUT_C fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information on this bit's operation under this condition. In voltage output mode, this bit is set if, on Channel C, the dc-to-dc converter is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. In current output mode, this bit is set on Channel B if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX voltage). In this case, the IOUT_B fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information on this bit's operation under this condition. In voltage output mode, this bit is set if, on Channel B, the dc-to-dc converter is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. In current output mode, this bit is set on Channel A if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX voltage). In this case, the IOUT_A fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information on this bit's operation under this condition. In voltage output mode, this bit is set if, on Channel A, the dc-to-dc converter is unable to regulate to 15 V as expected. When this bit is set, it does not result in the FAULT pin going high. User toggle bit. This bit is set or cleared via the software register. This can be used to verify data communications if needed. Denotes a PEC error on the last data-word received over the SPI interface. This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel). This bit is set if the AD5755-1 core temperature exceeds approximately 150C. This bit is set if a fault is detected on the VOUT_D pin. This bit is set if a fault is detected on the VOUT_C pin. This bit is set if a fault is detected on the VOUT_B pin. This bit is set if a fault is detected on the VOUT_A pin. This bit is set if a fault is detected on the IOUT_D pin. This bit is set if a fault is detected on the IOUT_C pin. This bit is set if a fault is detected on the IOUT_B pin. This bit is set if a fault is detected on the IOUT_A pin.
DC-DCC
DC-DCB
DC-DCA
User Toggle PEC Error Ramp Active Over TEMP VOUT_D Fault VOUT_C Fault VOUT_B Fault VOUT_A Fault IOUT_D Fault IOUT_C Fault IOUT_B Fault IOUT_A Fault
Rev. A | Page 38 of 48
AD5755-1 DEVICE FEATURES
OUTPUT FAULT
The AD5755-1 is equipped with a FAULT pin, an active low open-drain output allowing several AD5755-1 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault scenarios: * The voltage at IOUT_x attempts to rise above the compliance range due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with windowed limits because this requires an actual output error before the FAULT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability. Thus, the FAULT output activates slightly before the compliance limit is reached. A short is detected on a voltage output pin. The shortcircuit current is limited to 16 mA or 8 mA, which is programmable by the user. If using the AD5755-1 in unipolar supply mode, a short-circuit fault may be generated if the output voltage is below 50 mV. An interface error is detected due to a PEC failure. See the Packet Error Checking section. If the core temperature of the AD5755-1 exceeds approximately 150C.
DAC DATA REGISTER DAC INPUT REGISTER DAC M REGISTER C REGISTER
09226-075
Figure 77. Digital Offset and Gain control
Although Figure 77 indicates a multiplier and adder for each channel, there is only one multiplier and one adder in the device, and they are shared among all four channels. This has implications for the update speed when several channels are updated at once (see Table 3). Each time data is written to the M or C register, the output is not automatically updated. Instead, the next write to the DAC channel uses these M and C values to perform a new calibration and automatically updates the channel. The output data from the calibration is routed to the DAC input register. This is then loaded to the DAC as described in the Theory of Operation section. Both the gain register and the offset register have 16 bits of resolution. The correct method to calibrate the gain/offset is to first calibrate out the gain and then calibrate the offset. The value (in decimal) that is written to the DAC input register can be calculated by
*
* *
The VOUT_x fault, IOUT_x fault, PEC error, and over TEMP bits of the status register are used in conjunction with the FAULT output to inform the user which one of the fault conditions caused the FAULT output to be activated.
Code DACRegister = D x
( M + 1) 216
+ C - 215
(1)
VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION
Under normal operation, the voltage output sinks/sources up to 12 mA and maintains specified operation. The maximum output current or short-circuit current is programmable by the user and can be set to 16 mA or 8 mA. If a short circuit is detected, the FAULT goes low and the relevant short CCT bit in the status register is set.
where: D is the code loaded to the DAC channel's input register. M is the code in the gain register (default code = 216 - 1). C is the code in the offset register (default code = 215).
STATUS READBACK DURING A WRITE
The AD5755-1 has the ability to read back the status register contents during every write sequence. This feature is enabled via the STATREAD bit in the main control register. This allows the user to continuously monitor the status register and act quickly in the case of a fault. When status readback during a write is enabled, the contents of the 16-bit status register (see Table 30) are output on the SDO pin, as shown in Figure 5. The AD5755-1 powers up with this feature disabled. When this is enabled, the normal readback feature is not available, except for the status register. To read back any other register, clear the STATREAD bit first before following the readback sequence. STATREAD can be set high again after the register read.
DIGITAL OFFSET AND GAIN CONTROL
Each DAC channel has a gain (M) and offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the DAC data register is operated on by a digital multiplier and adder controlled by the contents of the M and C registers. The calibrated DAC data is then stored in the DAC input register.
Rev. A | Page 39 of 48
AD5755-1
ASYNCHRONOUS CLEAR
CLEAR is an active high, edge-sensitive input that allows the output to be cleared to a preprogrammed 16-bit code. This code is user programmable via a per channel 16-bit clear code register. For a channel to clear, that channel must be enabled to be cleared via the CLR_EN bit in the channel's DAC control register. If the channel is not enabled to be cleared, then the output remains in its current state independent of the CLEAR pin level. When the CLEAR signal is returned low, the relevant outputs remain cleared until a new value is programmed. disabled, the user can still use the normal readback operation to monitor status register activity with PEC.
WATCHDOG TIMER
When enabled, an on-chip watchdog timer generates an alert signal if 0x195 has not been written to the software register within the programmed timeout period. This feature is useful to ensure that communication has not been lost between the MCU and the AD5755-1 and that these datapath lines are working properly (that is, SDIN, SCLK, and SYNC). If 0x195 is not received by the software register within the timeout period, the ALERT pin signals a fault condition. The ALERT signal is active high and can be connected directly to the CLEAR pin to enable a clear in the event that communication from the MCU is lost. The watchdog timer is enabled, and the timeout period (5 ms, 10 ms, 100 ms, or 200 ms) is set in the main control register (see Table 18 and Table 19).
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environments, the AD5755-1 offers the option of packet error checking based on an 8-bit cyclic redundancy check (CRC-8). The device controlling the AD5755-1 should generate an 8-bit frame check sequence using the polynomial C(x) = x8 + x2 + x1 + 1 This is added to the end of the data-word, and 32 bits are sent to the AD5755-1 before taking SYNC high. If the AD5755-1 sees a 32-bit frame, it performs the error check when SYNC goes high. If the check is valid, the data is written to the selected register. If the error check fails, the FAULT pin goes low and the PEC error bit in the status register is set. After reading the status register, FAULT returns high (assuming there are no other faults), and the PEC error bit is cleared automatically.
UPDATE ON SYNC HIGH SYNC
OUTPUT ALERT
The AD5755-1 is equipped with an ALERT pin. This is an active high CMOS output. The AD5755-1 also has an internal watchdog timer. When enabled, it monitors SPI communications. If 0x195 is not received by the software register within the timeout period, the ALERT pin goes active.
INTERNAL REFERENCE
The AD5755-1 contains an integrated +5 V voltage reference with initial accuracy of 5 mV maximum and a temperature drift coefficient of 10 ppm maximum. The reference voltage is buffered and externally available for use elsewhere within the system.
EXTERNAL CURRENT SETTING RESISTOR
SCLK MSB D23 SDIN 24-BIT DATA 24-BIT DATA TRANSFER--NO ERROR CHECKING LSB D0
SYNC
UPDATE AFTER SYNC HIGH ONLY IF ERROR CHECK PASSED
Referring to Figure 73, RSET is an internal sense resistor as part of the voltage-to-current conversion circuitry. The stability of the output current value over temperature is dependent on the stability of the value of RSET. As a method of improving the stability of the output current over temperature, an external 15 k low drift resistor can be connected to the RSET_x pin of the AD5755-1 to be used instead of the internal resistor, R1. The external resistor is selected via the DAC control register (see Table 20). Table 1 outlines the performance specifications of the AD5755-1 with both the internal RSET resistor and an external, 15 k RSET resistor. Using an external RSET resistor allows for improved performance over the internal RSET resistor option. The external RSET resistor specification assumes an ideal resistor; the actual performance depends on the absolute value and temperature coefficient of the resistor used. This directly affects the gain error of the output, and thus the total unadjusted error. To arrive at the gain/TUE error of the output with a particular external RSET resistor, add the percentage absolute error of the RSET resistor directly to the gain/TUE error of the AD5755-1 with the external RSET resistor, shown in Table 1 (expressed in % FSR).
SCLK MSB D31 SDIN 24-BIT DATA LSB D8 D7 8-BIT CRC D0
32-BIT DATA TRANSFER WITH ERROR CHECKING
Figure 78. PEC Timing
The PEC can be used for both transmit and receive of data packets. If status readback during a write is enabled, the PEC values returned during the status readback during a write operation should be ignored. If status readback during a write is
Rev. A | Page 40 of 48
09226-180
FAULT
FAULT PIN GOES HIGH IF ERROR CHECK FAILS
AD5755-1
HART
The AD5755-1 has four CHART pins, one corresponding to each output channels. A HART signal can be coupled into these pins. The HART signal appears on the corresponding current output, if the output is enabled. Table 31 shows the recommended input voltages for the HART signal at the CHART pin. If these voltages are used, the current output should meet the HART amplitude specifications. Figure 79 shows the recommended circuit for attenuating and coupling in the HART signal. Table 31. CHART Input Voltage to HART Output Current
RSET Internal RSET External RSET CHART Input Voltage 150 mV p-p 170 mV p-p
C1 CHARTx HART MODEM OUTPUT C2
09226-076
Table 32. Slew Rate Update Clock Options
SR_CLOCK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1
Current Output (HART) 1 mA p-p 1 mA p-p
Update Clock Frequency (Hz)1 64 k 32 k 16 k 8k 4k 2k 1k 500 250 125 64 32 16 8 4 0.5
Figure 79. Coupling HART Signal
A minimum capacitance of C1 + C2 is required to ensure that the 1.2 kHz and 2.2 kHz HART frequencies are not significantly attenuated at the output. The recommended values are C1 = 22 nF, C2 = 47 nF. Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART.
These clock frequencies are divided down from the 13 MHz internal oscillator. See Table 1, Figure 69, and Figure 70.
Table 33. Slew Rate Step Size Options
SR_STEP 000 001 010 011 100 101 110 111 Step Size (LSBs) 1 2 4 16 32 64 128 256
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5755-1 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load. To reduce the slew rate, this can be achieved by enabling the slew rate control feature. With the feature enabled via the SREN bit of the slew rate control register (see Table 26), the output, instead of slewing directly between two values, steps digitally at a rate defined by two parameters accessible via the slew rate control register, as shown in Table 26. The parameters are SR_CLOCK and SR_STEP. SR_CLOCK defines the rate at which the digital slew is updated, for example, if the selected update rate is 8 kHz, the output updates every 125 s. In conjunction with this, SR_STEP defines by how much the output value changes at each update. Together, both parameters define the rate of change of the output value. Table 32 and Table 33 outline the range of values for both the SR_CLOCK and SR_STEP parameters.
The following equation describes the slew rate as a function of the step size, the update clock frequency, and the LSB size:
Slew Time = Output Change Step Size x Update Clock Frequency x LSB Size
where: Slew Time is expressed in seconds. Output Change is expressed in amps for IOUT_x or volts for VOUT_x. When the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the DC-to-DC Converter Settling Time section for additional information). For example, if the CLEAR pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the clear channel is enabled to be cleared). If a number of channels are enabled for slew, care must be taken when asserting the CLEAR pin. If one of the channels is slewing when CLEAR is asserted, other channels may change directly to their clear values not under slew rate control. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range.
Rev. A | Page 41 of 48
AD5755-1
POWER DISSIPATION CONTROL
The AD5755-1 contains integrated dynamic power control using a dc-to-dc boost converter circuit, allowing reductions in power consumption from standard designs when using the part in current output mode. In standard current input module designs, the load resistor values can range from typically 50 to 750 . Output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. For example, in a 4 mA to 20 mA loop when driving 20 mA, a compliance voltage of >15 V is required. When driving 20 mA into a 50 load, only 1 V compliance is required. The AD5755-1 circuitry senses the output voltage and regulates this voltage to meet compliance requirements plus a small headroom voltage. The AD5755-1 is capable of driving up to 24 mA through a 1 k load. output disabled, the converter regulates the VBOOST_x supply to +15 V (5%). In current output mode with the output disabled, the converter regulates the VBOOST_x supply to 7.4 V (5%). Within a channel, the VOUT_x and IOUT_x stages share a common VBOOST_x supply so that the outputs of the IOUT_x and VOUT_x stages can be tied together.
DC-to-DC Converter Settling Time
When in current output mode, the settling time for a step greater than ~1 V (IOUT x RLOAD) is dominated by the settling time of the dc-to-dc converter. The exception to this is when the required voltage at the IOUT_x pin plus the compliance voltage is below 7.4 V (5%). A typical plot of the output settling time can be found in Figure 49. This plot is for a 1 k load. The settling time for smaller loads is faster. The settling time for current steps less than 24 mA is also faster.
DC-to-DC Converter VMAX Functionality
The maximum VBOOST_x voltage is set in the dc-to-dc control register (23 V, 24.5 V, 27 V, or 29.5 V; see Table 25). On reaching this maximum voltage, the dc-to-dc converter is disabled, and the VBOOST_x voltage is allowed to decay by ~0.4 V. After the VBOOST_x voltage has decayed by ~0.4 V, the dc-to-dc converter is reenabled, and the voltage ramps up again to VMAX, if still required. This operation is shown in Figure 81.
29.6 29.5
VMAX DC_DC BIT
0mA TO 24mA RANGE, 24mA OUTPUT OUTPUT UNLOADED
DC-TO-DC CONVERTERS
The AD5755-1 contains four independent dc-to-dc converters. These are used to provide dynamic control of the VBOOST supply voltage for each channel (see Figure 73). Figure 80 shows the discreet components needed for the dc-to-dc circuitry, and the following sections describe component selection and operation of this circuitry.
AVCC CIN 10F LDCDC 10H SWx DDCDC CDCDC 4.7F RFILTER 10 VBOOST_X
09226-077
CFILTER 0.1F
29.4
VBOOST_x VOLTAGE (mV)
Figure 80. DC-to-DC Circuit
29.3 29.2 29.1 29.0 28.9 28.8 28.7
DC-DCx BIT = 0
09226-183
Table 34. Recommended DC-to-DC Components
Symbol LDCDC CDCDC DDCDC Component XAL4040-103 GRM32ER71H475KA88L PMEG3010BEA Value 10 H 4.7 F 0.38 VF Manufacturer Coilcraft(R) Murata NXP
DC-DCx BIT = 1
DC-DCMaxV = 11 (29.5V)
fSW = 410kHz
TA = 25C
It is recommended to place a 10 , 100 nF low-pass RC filter after CDCDC. This consumes a small amount of power but reduces the amount of ripple on the VBOOST_x supply.
28.6
0 0.5 1.0 1.5 2.0 2.5 TIME (ms) 3.0 3.5
4.0
DC-to-DC Converter Operation
The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step up an AVCC input of 4.5 V to 5.5 V to drive the AD5755-1 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous; that is, they require an external Schottky diode.
Figure 81. Operation on Reaching VMAX
As can be seen in Figure 81, the DC-DCx bit in the status register asserts when the AD5755-1 is ramping to the VMAX value but deasserts when the voltage is decaying to VMAX - ~0.4 V.
DC-to-DC Converter On-Board Switch
The AD5755-1 contains a 0.425 internal switch. The switch current is monitored on a pulse by pulse basis and is limited to 0.8 A peak current.
DC-to-DC Converter Switching Frequency and Phase
The AD5755-1 dc-to-dc converter switching frequency can be selected from the dc-to-dc control register. The phasing of the channels can also be adjusted so that the dc-to-dc converter can clock on different edges (see Table 25). For typical applications, a 410 kHz frequency is recommended. At light loads (low output
DC-to-DC Converter Output Voltage
When a channel current output is enabled, the converter regulates the VBOOST_x supply to 7.4 V (5%) or (IOUT x RLOAD + Headroom), whichever is greater (see Figure 53 for a plot of headroom supplied vs. output current). In voltage output mode with the
Rev. A | Page 42 of 48
AD5755-1
current and small load resistor), the dc-to-dc converter enters a pulse-skipping mode to minimize switching power dissipation. component. For the AD5755-1, a low ESR tantalum or ceramic capacitor of 10 F is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. X5R or X7R dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. Care must be taken if selecting a tantalum capacitor to ensure a low ESR value.
DC-to-DC Converter Inductor Selection
For typical 4 mA to 20 mA applications, a 10 H inductor (such as the XAL4040-103 from Coilcraft), combined with a switching frequency of 410 kHz, allows up to 24 mA to be driven into a load resistance of up to 1 k with an AVCC supply of 4.5 V to 5.5 V. It is important to ensure that the inductor is able to handle the peak current without saturating, especially at the maximum ambient temperature. If the inductor enters into saturation mode, it results in a decrease in efficiency. The inductance value also drops during saturation and may result in the dc-to-dc converter circuit not being able to supply the required output power.
AICC SUPPLY REQUIREMENTS--STATIC
The dc-to-dc converter is designed to supply a VBOOST_x voltage of VBOOST = IOUT x RLOAD + Headroom See Figure 53 for a plot of headroom supplied vs. output voltage. This means that, for a fixed load and output voltage, the dc-to-dc converter output current can be calculated by the following formula: (2)
DC-to-DC Converter External Schottky Selection
The AD5755-1 requires an external Schottky for correct operation. Ensure that the Schottky is rated to handle the maximum reverse breakdown expected in operation and that the rectifier maximum junction temperature is not exceeded. The diode average current is approximately equal to the ILOAD current. Diodes with larger forward voltage drops result in a decrease in efficiency.
AI CC =
Power Out Efficiency x AVCC
=
I OUT x VBOOST VBOOST x AVCC
(3)
where: IOUT is the output current from IOUT_x in amps. VBOOST is the efficiency at VBOOST_x as a fraction (see Figure 55 and Figure 56).
DC-to-DC Converter Compensation Capacitors
As the dc-to-dc converter operates in DCM, the uncompensated transfer function is essentially a single-pole transfer function. The pole frequency of the transfer function is determined by the dc-to-dc converter's output capacitance, input and output voltage, and output load. The AD5755-1 uses an external capacitor in conjunction with an internal 150 k resistor to compensate the regulator loop. Alternatively, an external compensation resistor can be used in series with the compensation capacitor, by setting the DC-DC Comp bit in the dc-to-dc control register. In this case, a ~50 k resistor is recommended. A description of the advantages of this can be found in the AICC Supply Requirements--Slewing section. For typical applications, a 10 nF dc-to-dc compensation capacitor is recommended.
AICC SUPPLY REQUIREMENTS--SLEWING
The AICC current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc-to-dc converter. This transient current can be quite large (see Figure 82), although the methods described in the Reducing AICC Current Requirements section can reduce the requirements on the AVCC supply. If not enough AICC current can be provided, the AVCC voltage drops. Due to this AVCC drop, the AICC current required to slew increases further. This means that the voltage at AVCC drops further (see Equation 3) and the VBOOST_x voltage, and thus the output voltage, may never reach its intended value. Because this AVCC voltage is common to all channels, this may also affect other channels.
0.8 0.7 0.6
AICC CURRENT (A) IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V)
09226-184
DC-to-DC Converter Input and Output Capacitor Selection
The output capacitor affects ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which the channel output current can rise. The ripple voltage is caused by a combination of the capacitance and equivalent series resistance (ESR) of the capacitor. For the AD5755-1, a ceramic capacitor of 4.7 F is recommended for typical applications. Larger capacitors or paralleled capacitors improve the ripple at the expense of reduced slew rate. Larger capacitors also impact the AVCC supplies current requirements while slewing (see the AICC Supply Requirements--Slewing section). This capacitance at the output of the dc-to-dc converter should be >3 F under all operating conditions. The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR
Rev. A | Page 43 of 48
30
25
0.5 0.4 0.3
0mA TO 24mA RANGE 1k LOAD fSW = 410kHz INDUCTOR = 10H (XAL4040-103) TA = 25C
20
15
10
0.2 0.1 0 AICC IOUT VBOOST 0 0.5 1.0 1.5 TIME (ms) 2.0 2.5
5
0
Figure 82. AICC Current vs. Time for 24 mA Slew with Internal Compensation Resistor
AD5755-1
There are two main methods that can be used to reduce the AICC current requirements. One method is to add an external compensation resistor, and the other is to use slew rate control. Both of these methods can be used in conjunction. A compensation resistor can be placed at the COMPDCDC_x pin in series with the 10 nF compensation capacitor. A 51 k external compensation resistor is recommended. This compensation increases the slew time of the current output but eases the AICC transient current requirements. Figure 83 shows a plot of AICC current for a 24 mA step through a 1 k load when using a 51 k compensation resistor. This method eases the current requirements through smaller loads even further, as shown in Figure 84.
0.8 0.7 0.6
AICC CURRENT (A) IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V)
0.7 0.6
AICC IOUT VBOOST
AICC CURRENT (A)
0mA TO 24mA RANGE 500 LOAD fSW = 410kHz INDUCTOR = 10H (XAL4040-103) TA = 25C
28 24 20 16 12 8 4 0
0.5 0.4 0.3 0.2 0.1 0
IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V) IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V)
09226-187 09226-186
Reducing AICC Current Requirements
0.8
32
0
0.5
1.0
1.5 TIME (ms)
2.0
2.5
0mA TO 24mA RANGE 1k LOAD fSW = 410kHz INDUCTOR = 10H (XAL4040-103) TA = 25C
32 28 24 20 16 12 8
Figure 84. AICC Current vs. Time for 24 mA Through 500 Slew with External 51 k Compensation Resistor
0.5 0.4 0.3 0.2 0.1 0 AICC IOUT VBOOST 0 0.5 1.0 1.5 TIME (ms) 2.0
4 0 2.5
Using slew rate control can greatly reduce the AVCC supplies current requirements, as shown in Figure 85. When using slew rate control, attention should be paid to the fact that the output cannot slew faster than the dc-to-dc converter. The dc-to-dc converter slews slowest at higher currents through large (for example, 1 k) loads. This slew rate is also dependent on the configuration of the dc-to-dc converter. Two examples of the dc-to-dc converter output slew are shown in Figure 83 and Figure 84 (VBOOST corresponds to the dc-to-dc converter's output voltage).
0.8 0.7 0.6 0mA TO 24mA RANGE 1k LOAD fSW = 410kHz INDUCTOR = 10H (XAL4040-103) TA = 25C AICC IOUT VBOOST
09226-185
32 28 24 20 16 12 8 4 0
AICC CURRENT (A)
Figure 83. AICC Current vs. Time for 24 mA Through 1 k Slew with External 51 k Compensation Resistor
0.5 0.4 0.3 0.2 0.1 0
0
1
2
3 TIME (ms)
4
5
6
Figure 85. AICC Current vs. Time for 24 mA Slew with Slew Rate Control
Rev. A | Page 44 of 48
AD5755-1 APPLICATIONS INFORMATION
VOLTAGE AND CURRENT OUTPUT RANGES ON THE SAME TERMINAL
When using a channel of the AD5755-1, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. There is no conflict with tying the two output pins together because only the voltage output or the current output can be enabled at any one time. When the current output is enabled, the voltage output is in tristate mode, and when the voltage output is enabled, the current output is in tristate mode. For this operation, the POC pin must be tied low and the POC bit in the main control register set to 0, or, if the POC pin is tied high, the POC bit in the main control register must be set to 1 before the current output is enabled. As shown in the Absolute Maximum Ratings section, the output tolerances are the same for both the voltage and current output pins. The +VSENSE_x connections are buffered so that current leakage into these pins is negligible when in current output mode. channels at zero scale, the full-scale error is 0.025%. Similarly, if only one channel is enabled in current output mode with the internal RSET, the full-scale error is 0.025% FSR + 0.075% FSR = 0.1% FSR.
PRECISION VOLTAGE REFERENCE SELECTION
To achieve the optimum performance from the AD5755-1 over its full operating temperature range, a precision voltage reference must be used. Thought should be given to the selection of a precision voltage reference. The voltage applied to the reference inputs is used to provide a buffered reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device. There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift, and output voltage noise. Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. The trim adjustment can be used at any temperature to trim out any error. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of a reference's output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage to ambient temperature. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET design) produce low output noise in the 0.1 Hz to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise.
CURRENT OUTPUT MODE WITH INTERNAL RSET
When using the internal RSET resistor in current output mode, the output is significantly affected by how many other channels using the internal RSET are enabled and by the dc crosstalk from these channels. The internal RSET specifications in Table 1 are for all channels enabled with the internal RSET selected and outputting the same code. For every channel enabled with the internal RSET, the offset error decreases. For example, with one current output enabled using the internal RSET, the offset error is 0.075% FSR. This value decreases proportionally as more current channels are enabled; the offset error is 0.056% FSR on each of two channels, 0.029% on each of three channels, and 0.01% on each of four channels. Similarly, the dc crosstalk when using the internal RSET is proportional to the number of current output channels enabled with the internal RSET. For example, with the measured channel at 0x8000 and one channel going from zero to full scale, the dc crosstalk is -0.011% FSR. With two channels going from zero to full scale, it is -0.019% FSR, and with all three other channels going from zero to full scale, it is -0.025% FSR. For the full-scale error measurement in Table 1, all channels are at 0xFFFF. This means that, as any channel goes to zero scale, the full-scale error increases due to the dc crosstalk. For example, with the measured channel at 0xFFFF and three Table 35. Recommended Precision References
Part No. ADR445 ADR02 ADR435 ADR395 AD586 Initial Accuracy (mV Maximum) 2 3 2 5 2.5 Long-Term Drift (ppm Typical) 50 50 40 50 15
Temperature Drift (ppm/C Maximum) 3 3 3 9 10
Rev. A | Page 45 of 48
0.1 Hz to 10 Hz Noise (V p-p Typical) 2.25 10 8 8 4
AD5755-1
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, a capacitor may be required between IOUT_x and AGND to ensure stability. A 0.01 F capacitor between IOUT_x and AGND ensures stability of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5755-1. There is no maximum capacitance limit for the current output of the AD5755-1.
SPORT_TFS SPORT_TSCK SPORT_DTO
AD5755-1
SYNC SCLK SDIN
ADSP-BF527
09226-080
GPIO0
LDAC
Figure 87. AD5755-1-to-ADSP-BF527 SPORT Interface
TRANSIENT VOLTAGE PROTECTION
The AD5755-1 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5755-1 from excessively high voltage transients, external power diodes and a surge current limiting resistor are required, as shown in Figure 86. The two protection diodes and resistor must have appropriate power ratings. Further protection can be provided with transient voltage suppressors or transorbs; these are available as both unidirectional suppressors (protect against positive high voltage transients) and bidirectional suppressors (protect against both positive and negative high voltage transients) and are available in a wide range of standoff and breakdown voltage ratings. It is recommended that all field connected nodes be protected.
AVDD
LAYOUT GUIDELINES
Grounding
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5755-1 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5755-1 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The GNDSWx and ground connection for the AVCC supply are referred to as PGND. PGND should be confined to certain areas of the board, and the PGND-to-AGND connection should be made at one point only.
Supply Decoupling
VBOOST_x
AD5755-1
GND
IOUT_x
RP RLOAD
Figure 86. Output Transient Voltage Protection
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5755-1 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire minimum interface consisting of a clock signal, a data signal, and a latch signal. The AD5755-1 requires a 24-bit data-word with data valid on the falling edge of SCLK. The DAC output update is initiated on either the rising edge of LDAC or, if LDAC is held low, on the rising edge of SYNC. The contents of the registers can be read using the readback function.
The AD5755-1 should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and low effective series inductance (ESL), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
09226-079
Traces
The power supply lines of the AD5755-1 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best but not always possible with a double-sided board. In this technique, the component
AD5755-1-TO-ADSP-BF527 INTERFACE
The AD5755-1 can be connected directly to the SPORT interface of the ADSP-BF527, an Analog Devices, Inc., Blackfin(R) DSP. Figure 87 shows how the SPORT interface can be connected to control the AD5755-1.
Rev. A | Page 46 of 48
AD5755-1
side of the board is dedicated to ground plane, whereas signal traces are placed on the solder side.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. Isocouplers provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5755-1 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 88 shows a 4-channel isolated interface to the AD5755-1 using an ADuM1400. For more information, visit www.analog.com.
MICROCONTROLLER SERIAL CLOCK OUT SERIAL DATA OUT SYNC OUT
DC-to-DC Converters
To achieve high efficiency, good regulation, and stability, a welldesigned printed circuit board layout is required. Follow these guidelines when designing printed circuit boards (see Figure 80): * * * Keep the low ESR input capacitor, CIN, close to AVCC and PGND. Keep the high current path from CIN through the inductor, LDCDC, to SWX and PGND as short as possible. Keep the high current path from CIN through LDCDC and the rectifier, DDCDC, to the output capacitor, CDCDC, as short as possible. Keep high current traces as short and as wide as possible. The path from CIN through the inductor, LDCDC, to SWX and PGND should be able to handle a minimum of 1 A. Place the compensation components as close as possible to COMPDCDC_x. Avoid routing high impedance traces near any node connected to SWx or near the inductor to prevent radiated noise injection.
ADuM1400*
VIA ENCODE DECODE VOA TO SCLK
VIB
ENCODE
DECODE
VOB
TO SDIN
*
VIC
ENCODE
DECODE
VOC
TO SYNC
* *
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 88. Isolated Interface
Rev. A | Page 47 of 48
09226-081
CONTROL OUT
VID
ENCODE
DECODE
VOD
TO LDAC
AD5755-1 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
48 PIN 1 INDICATOR 49 64 1
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
7.25 7.10 SQ 6.95
0.50 0.40 0.30 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
33 32
16 17
7.50 REF
0.25 MIN
1.00 0.85 0.80
SEATING PLANE
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 89. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm x 9 mm Body, Very Thin Quad (CP-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 AD5755-1ACPZ AD5755-1ACPZ-REEL7 EVAL-AD5755-1SDZ
1
Resolution (Bits) 16 16
Temperature Range -40C to +105C -40C to +105C
Package Description 64-lead LFCSP_VQ 64-lead LFCSP_VQ Evaluation Board
Package Option CP-64-3 CP-64-3
Z = RoHS Compliant Part.
(c)2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09226-0-5/11(A)
Rev. A | Page 48 of 48
080108-C

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